Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange).

Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

Abstract: Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are disclosed. An example apparatus includes an instantaneous mismatch estimator that uses an output of an interleaved analog to digital converter to identify a mismatch estimate between two or more component analog to digital converters of the interleaved analog to digital converter. An integrity monitor is to cause the instantaneous mismatch estimator to avoid incorrectly providing the mismatch estimate to a filter, the integrity monitor to instruct the filter to remove the mismatch estimate when the mismatch estimate is detected to be inaccurate.

Abstract: A system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.

Abstract: A system. The system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.

Abstract: Several methods and systems for location estimation are disclosed. In an embodiment, the method includes performing a primary wireless scan to identify a first set of access points at a user location associated with a first user location estimate. A secondary wireless scan is performed at pre-defined time intervals subsequent to the primary wireless scan. A set of access points is identified corresponding to each secondary wireless scan. The method further comprises detecting a presence or an absence of user motion based on a number of shared access points between the first set of access points and a set of access points corresponding to each secondary wireless scan. A current user location is estimated to be the first user location estimate if the user motion is detected to be absent, or a second user location estimate computed based on geolocation signals if the user motion is detected to be present.

Abstract: Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are disclosed. An example apparatus includes an instantaneous mismatch estimator that uses an output of an interleaved analog to digital converter to identify a mismatch estimate between two or more component analog to digital converters of the interleaved analog to digital converter. An integrity monitor is to cause the instantaneous mismatch estimator to avoid incorrectly providing the mismatch estimate to a filter, the integrity monitor to instruct the filter to remove the mismatch estimate when the mismatch estimate is detected to be inaccurate.

Abstract: Several methods and systems for location estimation are disclosed. In an embodiment, the method includes performing a primary wireless scan to identify a first set of access points at a user location associated with a first user location estimate. A secondary wireless scan is performed at pre-defined time intervals subsequent to the primary wireless scan. A set of access points is identified corresponding to each secondary wireless scan. The method further comprises detecting a presence or an absence of user motion based on a number of shared access points between the first set of access points and a set of access points corresponding to each secondary wireless scan. A current user location is estimated to be the first user location estimate if the user motion is detected to be absent, or a second user location estimate computed based on geolocation signals if the user motion is detected to be present.

Abstract: A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone. The system can also include a frequency domain estimator that determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone. The system can further include an averaging filter that averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate.

Abstract: A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.

Abstract: A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone. The system can also include a frequency domain estimator that determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone. The system can further include an averaging filter that averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate.

Abstract: A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.