Patent number: 6286128
Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
Type:
Grant
Filed:
June 12, 1998
Date of Patent:
September 4, 2001
Assignee:
Monterey Design Systems, Inc.
Inventors:
Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li, Robert Eugene Shortt, Christopher Dunn, David Gluss, Dennis Yamamoto, Dinesh Gaitonde, Douglas B. Boyle, Emre Tuncer, Eric McCaughrin, Feroze Peshotan Taraporevala, Gary K. Yeap, James S. Koford, Joseph T. Rahmeh, Lilly Shieh, Salil R. Raje, Sam Jung Kim, Satamurthy Pullela, Yau-Tsun Steven Li, Tong Gao
