Patents by Inventor Sateh M. Jalaleddine

Sateh M. Jalaleddine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7368994
    Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 6, 2008
    Assignee: Agere Systems, Inc.
    Inventors: Stephen J Franck, Sateh M Jalaleddine
  • Patent number: 7151410
    Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: December 19, 2006
    Assignee: Agere Systems Inc.
    Inventors: Stephen J. Franck, Sateh M. Jalaleddine
  • Patent number: 6924674
    Abstract: A folded cascode device senses the drain current of a source follower, and a current mirror device multiplies the sensed drain current for application to an output load. The source follower and the current mirror device are preferably of the same type (e.g., both NMOS). The resulting composite source follower provides relatively wide bandwidth at relatively low power. The folded cascode allows (NMOS) source and sink control. Using current mirror feedback reduces the stability problems associated with other solutions that rely on a voltage feedback stage. Composite source followers of the present invention can be used in any traditional buffer applications, such as in operational amplifiers, regulators, or high-speed signal paths.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: August 2, 2005
    Assignee: Agere Systems Inc.
    Inventors: Sateh M. Jalaleddine, Suharli Tedja
  • Patent number: 6236582
    Abstract: An current share controller detects a power converter module having the lowest supply current. That lowest supply current converter module is selected to be the system master. The current share controller is configured such that shared devices within the system can hot-swap capability. An output voltage loop amplifier includes an opto-coupler driver. The voltage loop amplifier compensation is compatible with conventional TL431 shunt regulators. This allows a power supply system to balance supply current between multiple supply modules with an eight pin load balancer configuration.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: May 22, 2001
    Assignee: Micro Linear Corporation
    Inventor: Sateh M. Jalaleddine