Patents by Inventor Sathaiya Mahaveer DHANYAKUMAR
Sathaiya Mahaveer DHANYAKUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063263Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min SHEN, Zhiqiang WU
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Patent number: 11843032Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.Type: GrantFiled: March 30, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Siang Lan, Sathaiya Mahaveer Dhanyakumar, Tzer-Min Shen, Zhiqiang Wu
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Publication number: 20230369335Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith KHADERBAD, Sathaiya Mahaveer DHANYAKUMAR, Huicheng CHANG, Keng-Chu LIN
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Patent number: 11776960Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.Type: GrantFiled: August 30, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Sathaiya Mahaveer Dhanyakumar, Huicheng Chang, Keng-Chu Lin
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Publication number: 20230062940Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith KHADERBAD, Sathaiya Mahaveer Dhanyakumar, Huicheng Chang, Keng-Chu Lin
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Publication number: 20230068065Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.Inventors: Mrunal Abhijith KHADERBAD, Sathaiya Mahaveer DHANYAKUMAR, Huicheng CHANG, Keng-Chu LIN, Winnie Victoria Wei-Ning CHEN
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Publication number: 20220320281Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.Type: ApplicationFiled: March 30, 2021Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min SHEN, Zhiqiang WU