Abstract: An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.

Abstract: Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

Abstract: Compute complexes, base dies, and methods related to leveraging reticle stitching for improved device interconnects are discussed. A base die includes first and second regions having device layers, lower level metallization layers, and through vias fabricated using the same reticles. In the first region, a first subset of the through vias are contacted by higher metallization layers and, in the second region, a second distinct subset of the through vias are contacted by higher metallization layers such that the first and second metallization layers provide unique routing through vias having shared layouts and relative locations in the first and second regions.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Abstract: Embodiments disclosed herein include memory architectures with stacked memory dies. In an embodiment, an electronic device comprises a base die and an array of memory dies over and electrically coupled to the base die. In an embodiment, the array of memory dies comprise caches. In an embodiment, a compute die is over and electrically coupled to the array of memory dies. In an embodiment, the compute die comprises a plurality of execution units.

Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

Abstract: Provided herein are schemes for reducing leakage in dynamic circuits during sleep modes.

Abstract: The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.

Abstract: A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

Abstract: In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

Abstract: The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.

Abstract: Provided herein are schemes for reducing leakage in dynamic circuits during sleep modes.