Abstract: A memory system and search method are provided for searching a multi-field longest prefix match (LPM) in a search term. The method provides a first LPM rule memory, where an LPM rule includes explicitly defined bit values in at least the n most significant bit (MSB) positions in a field of digital information, where n is an integer greater than or equal to 0. The method accepts a search term and compares at least a first field in the search term to subset rules structured in a sorted search tree for a first field organized as a LPM rule in the first LPM memory. When an explicit match is not found to the subset rules, the first field in the search term is compared to superset rules for the first field in the first LPM memory. As a final step, the method performs an instruction associated with a matching rule.

Abstract: A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

Abstract: A method is provided for pre-fetching packet data prior to processing. The method accepts a plurality of packets and writes each packet into a memory. A message is derived for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory. Each message is added to a tail of a first-in first-out (FIFO) queue. A pre-fetch module examines a first message, if the first message reaches a first capacity threshold of the FIFO queue. If the first message reaches the first capacity threshold, the pre-fetch module reads a first packet associated with the first message, from the memory, and the first packet is loaded into cache memory. A processor reads the first message from a head of the FIFO queue, and in response to reading the first message, reads the previously loaded first packet from cache memory.

Abstract: System and method for searching a data structure are disclosed. The method includes providing a data structure that includes a plurality of data entries stored in an external random access memory (RAM) and a portion of the data structure is stored in an internal cache memory, performing one or more hash functions on each entry of the data structure to generate an encoding that maps to a location in the external RAM, maintaining a count of encodings that map to the location in the external RAM, receiving a search string, performing the one or more hash functions on the search string to generate an index to the count of encodings, and searching the data structure in accordance with the count of encodings stored in the internal cache memory and in the external RAM.

Abstract: System and method for controlling updates of a data structure are disclosed. In one embodiment, the method includes providing a data structure that includes a hierarchically arranged set of nodes and branches, and each node has two or less branches, recording a total number of nodes in the data structure, determining whether to update the data structure according to one or more triggering conditions, generating an updated data structure in response to the one or more triggering conditions, and storing the updated data structure in a memory. The method of recording a total number of nodes includes incrementing a count of the total number of nodes by one when a new node is added to the data structure, and decrementing a count of the total number of nodes by one when a node is removed from the data structure.

Abstract: In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.

Abstract: A system and method are provided for the cut-through encryption of packets transmitted via a plurality of input/output (IO) ports. A system-on-chip is provided with a first plurality of input first-in first out (FIFO) memories, an encryption processor, and a first plurality of output FIFOs, each associated with a corresponding input FIFO. Also provided is a first plurality of IO ports, each associated with a corresponding output FIFO. At a tail of each input FIFO, packets from the SoC are accepted at a corresponding input data rate. Packet blocks are supplied to the encryption processor, from a head of each input FIFO, in a cut-through manner. The encryption processor supplies encrypted packet blocks to a tail of corresponding output FIFOs. The encrypted packet blocks are transmitted from each output FIFO, via a corresponding IO port at a port speed rate effectively equal to the corresponding input data rate.

Abstract: Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs.

Abstract: A method is provided for forwarding packets. Using a control plane state machine, addresses in a packet header are examined to derive a pointer value. The pointer value is used to access entries in a result database to identify routing information, a buffer pool ID associated with a location in memory, and a queue ID. A direct memory access (DMA) engine writes the packet into the memory location in response to the first message including the buffer pool ID. The QM prepares a second message associated with the packet, the second message including the routing information, the memory allocation in the buffer pool ID, and the queue ID. An operating system reads the second message, reads the packet from the memory allocation, modifies the packet header using the routing information, and writes the modified packet back into the memory allocation.

Abstract: System and method for updating a data structure are disclosed. In one embodiment, the method includes providing a data structure that includes a hierarchically arranged set of nodes and branches, and each node has two or less branches, retrieving a first data entry in the data structure via a first node in response to a first data access request, modifying the data structure to generate a first intermediate data structure that keeps the first node and creates a duplicate of the first node, and retrieving a second data entry in the data structure via the duplicate of first node in response to a second data access request. By maintaining at least the first node or a duplicate of the first node during a rebalancing operation of the data structure, the disclosed method supports accessing data entries associated with the first node during the rebalancing operation and therefore improves system performance.

Abstract: A data structure splitting method is provided for processing data using a minimum number of memory accesses. An SoC is provided with a with a central processing unit (CPU), a system memory, an on-chip memory (OCM), and a network interface including an embedded direct memory access (DMA). The network interface accepts a data structure with a header and a payload. The DMA writes the payload in the system memory, and the header in the OCM. The network interface DMA notifies the CPU of the header address in the OCM. The CPU reads the header in the OCM, performs processing instructions, and writes the processed header in the OCM. The CPU sends the address of the processed header in OCM to the network interface DMA. The network interface DMA reads the processed header from the OCM and sends a data structure with the processed header and the payload.

Abstract: A system and method are provided for residence time calculations in a network communications local device. A network interface module in the local device receives a first packet from a network-connected remote device. A timing module in the local device records an arrival time of the first packet with respect to a local reference clock. The timing module tracks adjustments in the local reference clock and records a known departure time, with respect to the local reference clock, of when the first packet will be transmitted from the network interface. The timing module adds a residence time field to the first packet representing the difference between the arrival and departure times, taking into account adjustments in the local reference clock.

Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.

Abstract: In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.

Abstract: A method is provided for managing a transmit buffer using per priority pause flow control. An Ethernet transceiver generates packet descriptors identifying packets to be transmitted that are stored in memory. A priority is assigned to each descriptor and associated packet. Each descriptor is loaded into a queue having a queue priority associated with the descriptor priority. In response to accessing a first descriptor, output from a selected first priority queue, a first packet associated with the first descriptor is fetched into a transmit buffer from the memory. If subsequent to fetching the first packet, a per priority flow control message is received pausing first priority packets, the first packet is flushed from the transmit buffer. Then, a second descriptor is accessed from a selected second priority queue, and a second packet associated with the second descriptor is fetched and transmitted from the transmit buffer.

Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.

Abstract: Methods and systems for deploying higher-bandwidth networks using lower-bandwidth capable network processing devices. This provides for Parallel Network processing units (PNPU) to work together to process higher bandwidths in networking systems. The methods involve the utilization of several low speed busses to achieve a higher throughput; a CRC generation technique; and improving the performance of such busses using synchronization techniques.