Abstract: An error correcting method for correcting an error of digital data is provided. The method includes a plurality of sub-frames including a plurality of block code words, including: extracting and aligning a block code word, which is included in a past sub-frame; and generating a redundant data block code word by use of a block code word, which is included in a latest sub-frame, and the aligned block code word, and adding the redundant data block code word to the latest sub-frame, wherein the redundant data block code word is used for generating a redundant data block code word, which is added to a next sub-frame.

Abstract: Flip-flop circuits FF1 to FF6 are each constructed as a pair of cascade connected latch circuits 21 and 22 in an arbitrarily combination. The latch circuits L1 and L2 each comprises an input stage push-pull circuit PP and an output stage hold circuit HD as CVSL circuit. The latch circuit L1 includes an input stage having two pairs of nMOSTs 2 to 5 receiving input data DP and DN inputted thereto and connected in series each and in parallel connection of the pairs and a pair of nMOSTs 1 to 6 receiving a clock CP inputted thereto and connected to the opposite sides of the parallel connection. The output stage hold circuit HD includes a CVSI circuit having two pairs of nMOSTs 7 and 10 and a pair of pMOSTs 12 and 13 and an nMOST 11 receiving a clock CN inputted thereto. Thus obtained flip-flop (FF) circuit permits construction of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.

Abstract: A gated clock type logic circuit is provided in which timing designing for a supply of a clock can be made easy and a period of time required for designing can be shortened. The gated clock type logic circuit has a gate circuit designed to allow a clock signal inputted in accordance with a level of a clock enabling signal to be passed or to be masked. An output of the gate circuit to control a latching timing of a latch circuit for receiving data is fed to a clock input terminal of the latch circuit. The gated clock type logic circuit is provided with a selector which receives an input data and an output data from the latch circuit and selects either of the input data or the output data by using a data enabling signal as a selecting signal and outputs it. An output from the selector is fed to a data input terminal of the latch circuit.

Abstract: Flip-flop circuits FF1 to FF6 are each constructed as a pair of cascade connected latch circuits 21 and 22 in an arbitrarily combination. The latch circuits L1 and L2 each comprises an input stage push-pull circuit PP and an output stage hold circuit HD as CVSL circuit. The latch circuit L1 includes an input stage having two pairs of nMOSTs 2 to 5 receiving input data DP and DN inputted thereto and connected in series each and in parallel connection of the pairs and a pair of nMOSTs 1 to 6 receiving a clock CP inputted thereto and connected to the opposite sides of the parallel connection. The output stage hold circuit HD includes a CVSI circuit having two pairs of nMOSTs 7 and 10 and a pair of pMOSTs 12 and 13 and an nMOST 11 receiving a clock CN inputted thereto. Thus obtained flip-flop (FF) circuit permits construction of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.

Abstract: An interconnection circuit having a circuit portion which is provided in one of two integrated semiconductors to be connected, for limiting the amplitude in voltage of the signal output from said one circuit, and another circuit portion which is provided in the other one of the two circuits, for discriminating the logic level of the signal input thereinto based on a threshold level set at an intermediate level between said amplitude. The amplitude of the logic signal transferred across the two circuits is thus compressed, thereby deereasing delay time for the signal to transfer between the two circuits.