Patents by Inventor Satoru Araki

Satoru Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11751484
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Satoru Araki
  • Patent number: 11751481
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Satoru Araki
  • Publication number: 20230245325
    Abstract: Provided is a moving object detection device including a storage medium storing computer-readable commands and a processor connected to the storage medium, the processor executing the computer-readable commands to: acquire image data including a plurality of frames representing a surrounding condition of a mobile object, which are photographed by a camera mounted in the mobile object in time series; calculate a difference image between the plurality of frames by calculating differences between the plurality of frames and binarizing the differences using a first value and a second value; extract a grid for which the density of pixels with the first value is equal to or larger than a first threshold value from among a plurality of grids set in the difference image; and detect the extracted grid as a moving object.
    Type: Application
    Filed: January 23, 2023
    Publication date: August 3, 2023
    Inventors: Satoru Araki, Gakuyo Fujimoto, Masamitsu Tsuchiya
  • Publication number: 20230245323
    Abstract: An object tracking device according to embodiments includes an image acquirer configured to acquire image data including a plurality of image frames captured in time series by an imager mounted on a mobile object, a recognizer configured to recognize an object from image data acquired by the image acquirer, an area setter configured to set an image area including an object recognized by the recognizer, and an object tracker configured to track the object on the basis of an amount of time-series change in an image area set by the area setter, in which the area setter sets a position and a size of an image area for tracking the object in the future image frame on the basis of the amount of time-series change in an image area including the object in the past image frame and behavior information of the mobile object.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 3, 2023
    Inventors: Satoru Araki, Masamitsu Tsuchiya
  • Publication number: 20230154532
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 18, 2023
    Inventors: Hiroshi YOSHIDA, Toshimasa NAMEKAWA, Satoru ARAKI, Etsuo FUKUDA, Tetsuo ENDOH
  • Patent number: 11631807
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 18, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Publication number: 20220037588
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 3, 2022
    Inventor: Satoru ARAKI
  • Publication number: 20220029092
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Application
    Filed: August 16, 2021
    Publication date: January 27, 2022
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Publication number: 20220028929
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Application
    Filed: August 16, 2021
    Publication date: January 27, 2022
    Inventor: Satoru ARAKI
  • Patent number: 11107978
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 31, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 11107974
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 31, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 11107979
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 31, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Patent number: 10930843
    Abstract: A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending along a first direction. The method further includes depositing, on the distinct instances of the first conductive material, a set of device layers. The method further includes electrically isolating distinct instances of the device layers to form spin orbit torque magnetic random access memory (SOT-MRAM) devices positioned on distinct instances of the first conductive material. The method further includes depositing, on the distinct instances of the device layers, a layer of a second conductive material and electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction. The second direction is different from the first direction.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 23, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 10930703
    Abstract: A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: February 23, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Michael Ryan, Satoru Araki, Andrew J. Walker
  • Patent number: 10784437
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 22, 2020
    Assignee: SPIN MEMORY, Inc.
    Inventor: Satoru Araki
  • Patent number: 10734573
    Abstract: A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 4, 2020
    Assignee: Spin Memory, Inc.
    Inventor: Satoru Araki
  • Publication number: 20200212296
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Publication number: 20200194666
    Abstract: A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending along a first direction. The method further includes depositing, on the distinct instances of the first conductive material, a set of device layers. The method further includes electrically isolating distinct instances of the device layers to form spin orbit torque magnetic random access memory (SOT-MRAM) devices positioned on distinct instances of the first conductive material. The method further includes depositing, on the distinct instances of the device layers, a layer of a second conductive material and electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction. The second direction is different from the first direction.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventor: Satoru Araki
  • Patent number: 10686009
    Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 16, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Michael Ryan, Satoru Araki, Andrew J. Walker
  • Patent number: 10658021
    Abstract: A magnetic storage device includes a plurality of first wires extending along a first direction and a plurality of second wires extending along a second direction different from the first direction. The plurality of second wires form a grid with the plurality of first wires. The magnetic storage device further includes a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the plurality of SOT-MRAM devices is disposed at a respective position on the grid. The magnetic storage device further includes write circuitry, including a transistor coupled to each respective first wire of the plurality of first wires, to apply a first write current along the respective first wire in the first direction, and readout circuitry to read a data value stored by a respective SOT-MRAM device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki