Abstract: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.

Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided.