Patents by Inventor Satoru Narioka

Satoru Narioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6181406
    Abstract: A liquid crystal display device has a liquid crystal panel wherein an opposite substrate includes a plurality of pillar-shaped spacers opposing scanning lines provided on an array substrate. The spacers have distal ends which contact the scanning lines with an opposite electrode of the opposing substrate being interposed between the distal ends and the scanning lines. Each of the distal ends of the spacers has a width smaller than the width of each scanning line. Pixel electrodes have notches which are formed in those of their side edges which are opposite to the scanning lines, such that the notches are located opposite to the distal ends of the spacers. The distance between the side edges of the pixel electrode and the scanning line opposing the side edges is larger at regions around the distal ends of the spacers than other regions.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: January 30, 2001
    Assignee: Kabushiki Kaisa Toshiba
    Inventors: Hirokazu Morimoto, Takaomi Tanaka, Tetsuya Nishino, Satoru Narioka
  • Patent number: 6036568
    Abstract: On the surface of an array substrate 60, a sealing material 64 is provided so as to surround a display region, and a plurality of spacers 66 are provided in the display region. The array substrate 60 and a counter substrate 62 are vacuum held to stages 20 and 18, respectively, so that the array substrate 60 and the counter substrate 62 face each other. In one of the stages, a recessed portion 26 facing the effective region of the counter substrate 62 is formed. By evacuating the recessed portion, the effective region of the counter substrate 62 is deflected so as to go away from the effective region of the array substrate 60. In this state, the peripheral portions of the array substrate 60 and the counter substrate 62 are panel aligned with each other via the sealing material 64. Subsequently, the counter substrate 62 is positioned with respect to the array substrate 60 by means of an X-Y-.theta. stage.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsunori Murouchi, Satoru Narioka, Tetsuya Nishino, Hirokazu Morimoto, Takaomi Tanaka, Tadashi Honda, Hiroshi Otaguro, Hironori Takabayashi, Toshitaka Nonaka