Patents by Inventor Satoru Yamane

Satoru Yamane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7057448
    Abstract: Disclosed is a variable output-type constant current source circuit capable of varying its output current in a stepwise manner without the complication in circuit configuration and the increase in size of a semiconductor circuit board for incorporating the circuit therein. The constant current source circuit comprises a first self-biasing type constant current circuit 3a configured such that transistors M1, M2 are operable to cooperatively supply a given voltage across a resistor RS to generate a stabilized current IR1. In order to vary the output current, the constant current source circuit includes a switching circuit 5 (transistor M5) connected in series to a series circuit connecting in series the transistor M1 and the resistor RS, and a second constant current circuit 4 connected in parallel to a series circuit connecting in series the transistor M1, the resistor RS and the transistor M5.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: June 6, 2006
    Assignee: Toko, Inc.
    Inventors: Hiroshi Tanigawa, Shuichi Nakamura, Satoru Yamane
  • Patent number: 6927559
    Abstract: Disclosed is a constant voltage power supply, which comprises an error amplifier VEA including a transistor M3, and a transistor M4 having the same ratio between channel width and channel length as that of the transistor M3. The gate and source of the transistor M4 are connected to the gate of a transistor M3 to form a current mirror circuit in conjunction with the transistor M3. Further, the drain of the transistor M4 is connected with a transistor M5 adapted to be switched in response to an external control signal Sg. For example, when the transistor M5 is in ON state, any signal amplification function of the transistor M3 is vanished away, and the gain of the error amplifier VEA is lowered. The circuit configuration for changing the gain of the error amplifier VEA makes it possible to strike a balance between high-speed response characteristic in an active mode and operational stability in a sleep mode, and reduce a circuit area required for being formed on an integrated circuit.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 9, 2005
    Assignee: Toko, Inc.
    Inventors: Hiroshi Tanigawa, Satoru Yamane
  • Publication number: 20040246046
    Abstract: Disclosed is a variable output-type constant current source circuit capable of varying its output current in a stepwise manner without the complication in circuit configuration and the increase in size of a semiconductor circuit board for incorporating the circuit therein. The constant current source circuit comprises a first self-biasing type constant current circuit 3a configured such that transistors M1, M2 are operable to cooperatively supply a given voltage across a resistor RS to generate a stabilized current IR1. In order to vary the output current, the constant current source circuit includes a switching circuit 5 (transistor M5) connected in series to a series circuit connecting in series the transistor M1 and the resistor RS, and a second constant current circuit 4 connected in parallel to a series circuit connecting in series the transistor M1, the resistor RS and the transistor M5.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 9, 2004
    Applicant: Toko, Inc.
    Inventors: Hiroshi Tanigawa, Shuichi Nakamura, Satoru Yamane
  • Publication number: 20040104712
    Abstract: Disclosed is a constant voltage power supply, which comprises an error amplifier VEA including a transistor M3, and a transistor M4 having the same ratio between channel width and channel length as that of the transistor M3. The gate and source of the transistor M4 are connected to the gate of a transistor M3 to form a current mirror circuit in conjunction with the transistor M3. Further, the drain of the transistor M4 is connected with a transistor M5 adapted to be switched in response to an external control signal Sg. For example, when the transistor M5 is in ON state, any signal amplification function of the transistor M3 is vanished away, and the gain of the error amplifier VEA is lowered. The circuit configuration for changing the gain of the error amplifier VEA makes it possible to strike a balance between high-speed response characteristic in an active mode and operational stability in a sleep mode, and reduce a circuit area required for being formed on an integrated circuit.
    Type: Application
    Filed: November 24, 2003
    Publication date: June 3, 2004
    Applicant: Toko, Inc.
    Inventors: Hiroshi Tanigawa, Satoru Yamane