Patents by Inventor Satoshi Hongo
Satoshi Hongo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411287Abstract: A semiconductor device includes a wiring layer; a first stacked body disposed on the wiring layer; a second stacked body disposed on the first stacked body in a stacking direction; and a first resin body disposed around a periphery of the first stacked body. The first stacked body includes a first pad electrically connected to the wiring layer, a first device layer electrically connected to the first pad, and a first electrode electrically connected to the first device layer. The second stacked body includes a second pad electrically connected to the first electrode and a second device layer electrically connected to the second pad. In the stacking direction, the first resin body is vertically located closer to the wiring layer than an interface between the first stacked body and the second stacked body.Type: ApplicationFiled: March 3, 2023Publication date: December 21, 2023Applicant: Kioxia CorporationInventors: Eiichi SHIN, Satoshi HONGO, Susumu YAMAMOTO, Yukio KATAMURA, Gen TOYOTA, Tsutomu FUJITA
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Publication number: 20230307415Abstract: According to one embodiment, a semiconductor device includes a base substrate with an interconnection layer and a plurality of chips stacked on the base substrate. A protective film is between each adjacent pair of chips in the plurality of chips stacked on the base substrate and on side surfaces of at least each chip in the plurality other than an uppermost chip in the stacked plurality of chips. A lowermost chip in the stacked plurality of chips has a metal pad electrically connected to the interconnection layer. Each chip in an adjacent pair of chips in the plurality of chips stacked on the base substrate has an electrode contacting an electrode of the other chip in the adjacent pair.Type: ApplicationFiled: August 30, 2022Publication date: September 28, 2023Inventors: Satoshi HONGO, Tatsuo MIGITA, Gen TOYOTA
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Publication number: 20230101002Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.Type: ApplicationFiled: March 14, 2022Publication date: March 30, 2023Applicant: Kioxia CorporationInventors: Gen TOYOTA, Satoshi HONGO, Tatsuo MIGITA, Susumu YAMAMOTO, Tsutomu FUJITA, Eiichi SHIN, Yukio KATAMURA, Hideki MATSUSHIGE, Kazuki TAKAHASHI
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Publication number: 20220375901Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.Type: ApplicationFiled: February 28, 2022Publication date: November 24, 2022Inventors: Susumu YAMAMOTO, Tsutomu FUJITA, Takeori MAEDA, Satoshi HONGO, Gen TOYOTA, Eiichi SHIN, Yukio KATAMURA
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Patent number: 11299742Abstract: The purpose of the present invention is to provide a breeding method for a plant having a blue flower color with a simpler blue color development controlling technique, without requiring complex mechanisms for blue color development that have been previously presented and techniques reproducing such mechanisms. Delphinidin-based anthocyanins, in which the both 3? and 5?-positions of the anthocyanin B-ring have been glycosylated, and flavone glycosides or flavonol glycosides as copigment are made to coexist in the cells of flower organ such as petals.Type: GrantFiled: March 13, 2017Date of Patent: April 12, 2022Assignee: SUNTORY HOLDINGS LIMITEDInventors: Naonobu Noda, Masayoshi Nakayama, Mitsuru Douzono, Satoshi Hongo, Ryutaro Aida, Yukihisa Katsumoto
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Patent number: 10870861Abstract: Provided are transformed chrysanthemum plants having blue flower color, their self-fertilized progenies or cross-fertilized progenies thereof, a vegetative propagated plants thereof, and a part, a tissue or a cell of the plant body. Anthocyanin 3?,5?-O-glucosyltransferase gene (CtA3?5?GT) derived from Clitoria ternatea and flavonoid 3?,5?-hydroxylase gene derived from Campanula (CamF3?5?H) are coexpressed in chrysanthemum petals.Type: GrantFiled: June 30, 2016Date of Patent: December 22, 2020Assignee: SUNTORY HOLDINGS LIMITEDInventors: Naonobu Noda, Ryutaro Aida, Satoshi Hongo, Sanae Sato, Yoshikazu Tanaka
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Publication number: 20200325486Abstract: The purpose of the present invention is to provide a breeding method for a plant having a blue flower color with a simpler blue color development controlling technique, without requiring complex mechanisms for blue color development that have been previously presented and techniques reproducing such mechanisms. Delphinidin-based anthocyanins, in which the both 3? and 5?-positions of the anthocyanin B-ring have been glycosylated, and flavone glycosides or flavonol glycosides as copigment are made to coexist in the cells of flower organ such as petals.Type: ApplicationFiled: March 13, 2017Publication date: October 15, 2020Applicant: SUNTORY HOLDINGS LIMITEDInventors: Naonobu NODA, Masayoshi NAKAYAMA, Mitsuru DOUZONO, Satoshi HONGO, Ryutaro AIDA, Yukihisa KATSUMOTO
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Publication number: 20200083175Abstract: A device includes a first semiconductor substrate and a second semiconductor substrate. A first insulating film is provided on a first face of the first semiconductor substrate. A first metal layer covers an inner surface of a first grove provided on the first insulating film. A first electrode is provided on the first metal layer and embedded in the first groove. The second semiconductor substrate has a second face facing the first face of the first semiconductor substrate. A second insulating film is provided on the second face of the second semiconductor substrate and is attached to the first insulating film. A second electrode is embedded in a second groove provided on the second insulating film and is connected to the first electrode. An end part of the first metal layer is recessed toward the first semiconductor substrate relative to a surface of the first insulating film.Type: ApplicationFiled: January 22, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Satoshi HONGO
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Publication number: 20190032066Abstract: Provided are transformed chrysanthemum plants having blue flower color, their self-fertilized progenies or cross-fertilized progenies thereof, a vegetative propagated plants thereof, and a part, a tissue or a cell of the plant body. Anthocyanin 3?,5?-O-glucosyltransferase gene (CtA3?5?GT) derived from Clitoria ternatea and flavonoid 3?,5?-hydroxylase gene derived from Campanula (CamF3?5?H) are coexpressed in chrysanthemum petals.Type: ApplicationFiled: June 30, 2016Publication date: January 31, 2019Inventors: Naonobu NODA, Ryutaro AIDA, Satoshi HONGO, Sanae SATO, Yoshikazu TANAKA
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Patent number: 9824025Abstract: An information processing system comprising a storage device and an information processing device, wherein the information processing device includes a data holding unit which holds first data, a first detection unit which detects a first state of access, and a transmission unit which transmits the first state of access detected by the first detection unit to the storage device, and the storage device includes a storage unit which stores second data, a reception unit which receives the first state of access transmitted from the transmission unit, a second detection unit which detects a second state of access, which is a state of access to the second data, and a control unit which rearranges the second data in the storage unit on the basis of the states of access.Type: GrantFiled: February 13, 2015Date of Patent: November 21, 2017Assignee: FUJITSU LIMITEDInventors: Atsushi Takada, Kazuo Mineno, Isamu Ooishi, Tetsuya Sano, Satoshi Hongo, Satoshi Matsumoto, Yasuhiko Kondo, Kazuhisa Hiramatsu, Makoto Iwadare
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Publication number: 20160035766Abstract: A semiconductor device such as, for example an imaging sensor, includes a semiconductor layer in which, for example, a photodiode may be formed. An insulation film is disposed on a surface of the semiconductor layer. The insulation film includes one or more wirings or wiring layers formed therein. A semiconductor support substrate is disposed on the insulation film. The semiconductor support substrate includes a first layer (or region) and a second layer (or region) that is between the insulation film and the first layer. The first layer has a bulk micro defect density that is higher than a bulk micro defect density of the second layer.Type: ApplicationFiled: February 17, 2015Publication date: February 4, 2016Inventors: Satoshi HONGO, Tsuyoshi MATSUMURA, Hiroaki ASHIDATE, Kazumasa TANIDA
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Publication number: 20150253994Abstract: An information processing system comprising a storage device and an information processing device, wherein the information processing device includes a data holding unit which holds first data, a first detection unit which detects a first state of access, and a transmission unit which transmits the first state of access detected by the first detection unit to the storage device, and the storage device includes a storage unit which stores second data, a reception unit which receives the first state of access transmitted from the transmission unit, a second detection unit which detects a second state of access, which is a state of access to the second data, and a control unit which rearranges the second data in the storage unit on the basis of the states of access.Type: ApplicationFiled: February 13, 2015Publication date: September 10, 2015Inventors: ATSUSHI TAKADA, Kazuo Mineno, Isamu Ooishi, Tetsuya Sano, Satoshi Hongo, Satoshi MATSUMOTO, Yasuhiko KONDO, Kazuhisa Hiramatsu, Makoto Iwadare
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Patent number: 9004337Abstract: According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.Type: GrantFiled: May 24, 2012Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hongo, Kenji Takahashi, Kazumasa Tanida
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Patent number: 8980671Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.Type: GrantFiled: February 8, 2012Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
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Patent number: 8822307Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.Type: GrantFiled: March 16, 2012Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8609511Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.Type: GrantFiled: August 29, 2011Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
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Publication number: 20130183810Abstract: According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.Type: ApplicationFiled: May 24, 2012Publication date: July 18, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi HONGO, Kenji Takahashi, Kazumasa Tanida
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Publication number: 20130062737Abstract: According to one embodiment, a semiconductor device comprises a device substrate, and a supporting substrate. The supporting substrate is joined onto the device substrate. The device substrate has a first groove in an outer circumferential portion on a joint surface side to the supporting substrate.Type: ApplicationFiled: March 23, 2012Publication date: March 14, 2013Inventors: Satoshi HONGO, Kazumasa Tanida, Kenji Takahashi
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Publication number: 20120329241Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.Type: ApplicationFiled: March 16, 2012Publication date: December 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi