Patents by Inventor Satoshi Ihida
Satoshi Ihida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150698Abstract: A cell culture device includes a substrate, a wire disposed on a main surface of the substrate, an insulating film disposed on the main surface of the substrate and having a part that overlaps the wire, and the electrodes disposed on the insulating film and having a part that overlaps the wire. The insulating film has a contact hole at a position overlapping the wire and the electrode. A plurality of grooves are formed on at least the surface of a part of the electrode that overlaps the contact hole.Type: ApplicationFiled: October 25, 2023Publication date: May 9, 2024Inventors: Chihiro TACHINO, Tomoko TERANISHI, Satoshi IHIDA, Takeshi HARA
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Publication number: 20230323266Abstract: A cell culture substrate includes a base, a first segment disposed on the base and occupying a part of one surface of the cell culture substrate, and a second segment disposed on the base and occupying another part of the one surface. The second segment is formed of a metal material and thus has a relatively higher surface free energy than the first segment formed of an inorganic material. The second segment is disposed such that a percentage of an area of the second segment in a total area of the first segment and the second segment increases in a gradation direction (first direction) along the one surface.Type: ApplicationFiled: March 17, 2023Publication date: October 12, 2023Inventors: Chihiro TACHINO, Takeshi HARA, Tomoko TERANISHI, Satoshi IHIDA
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Publication number: 20230023499Abstract: A cell culture apparatus includes: a substrate having a first surface; a pair of structures each having a wall surface intersecting the first surface, the wall surfaces facing each other; and an electrode disposed on the first surface and traversing a space between the wall surfaces, the electrode and each of the wail surfaces forming an angle other than 90 degrees.Type: ApplicationFiled: July 1, 2022Publication date: January 26, 2023Inventors: Manabu DAIO, TOMOKO TERANISHI, Satoshi IHIDA, CHIHIRO TACHINO
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Publication number: 20180201920Abstract: A phoresis device for moving a target object by dielectrophoresis is realized with use of a thin film transistor substrate. A phoresis device (1) includes a TFT substrate (10) which supports a muscle cell (T1) and a nerve cell (T2) and which is configured to form an electric field that causes dielectrophoresis. In the phoresis device (1), the muscle cell (T1) and the nerve cell (T2) are moved through application of a voltage to part of a plurality of transistors of the TFT substrate (10).Type: ApplicationFiled: July 13, 2016Publication date: July 19, 2018Inventors: Satoshi IHIDA, Agnes TIXIER MITA, Hiroshi TOSHIYOSHI
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Patent number: 9601074Abstract: Included are: refresh a rate changing section (15) for changing a refresh rate of a display panel (2) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel (2) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section (20) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.Type: GrantFiled: May 20, 2016Date of Patent: March 21, 2017Assignee: Sharp Kabushiki KaishaInventors: Akizumi Fujioka, Toshihiro Yanagi, Satoshi Ihida, Kazuki Takahashi, Taketoshi Nakano
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Publication number: 20160267870Abstract: Included are: refresh a rate changing section (15) for changing a refresh rate of a display panel (2) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel (2) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section (20) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: Akizumi FUJIOKA, Toshihiro YANAGI, Satoshi IHIDA, Kazuki TAKAHASHI, Taketoshi NAKANO
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Patent number: 9378697Abstract: Included are: refresh a rate changing section (15) for changing a refresh rate of a display panel (2) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel (2) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section (20) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.Type: GrantFiled: February 13, 2013Date of Patent: June 28, 2016Assignee: Sharp Kabushiki KaishaInventors: Akizumi Fujioka, Toshihiro Yanagi, Satoshi Ihida, Kazuki Takahashi, Taketoshi Nakano
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Publication number: 20140368492Abstract: Included are: refresh a rate changing section (15) for changing a refresh rate of a display panel (2) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel (2) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section (20) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.Type: ApplicationFiled: February 13, 2013Publication date: December 18, 2014Inventors: Akizumi Fujioka, Toshihiro Yanagi, Satoshi Ihida, Kazuki Takahashi, Taketoshi Nakano
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Patent number: 7990501Abstract: A method for manufacturing a transflective type LCD having a first substrate provided thereon with a plurality of scanning lines and a plurality of signal lines which are substantially perpendicular to each other and a switching element arranged near each of intersections between said scanning lines and said signal lines, includes forming a reflection region having a reflection electrode film and a transmission region having a transparent electrode film in each pixel surrounded by said scanning lines and said signal lines, a liquid crystal being sandwiched at a gap between said first substrate and a second substrate which is arranged opposite to said first substrate, and forming an organic film having irregularities thereon below said reflection electrode film and said transparent electrode film to substantially the same film thickness.Type: GrantFiled: October 15, 2010Date of Patent: August 2, 2011Assignee: NEC LCD Technologies, Ltd.Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
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Publication number: 20110027460Abstract: A method for manufacturing a transflective type LCD having a first substrate provided thereon with a plurality of scanning lines and a plurality of signal lines which are substantially perpendicular to each other and a switching element arranged near each of intersections between said scanning lines and said signal lines, includes forming a reflection region having a reflection electrode film and a transmission region having a transparent electrode film in each pixel surrounded by said scanning lines and said signal lines, a liquid crystal being sandwiched at a gap between said first substrate and a second substrate which is arranged opposite to said first substrate, and forming an organic film having irregularities thereon below said reflection electrode film and said transparent electrode film to substantially the same film thickness.Type: ApplicationFiled: October 15, 2010Publication date: February 3, 2011Applicant: NEC LCD Technologies, Ltd.Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
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Patent number: 7817229Abstract: In a transflective type LCD provided with a transparent region and a reflection region in each pixel, when an irregular film 11 is formed on an active matrix substrate 12 to form irregularities of a reflection electrode film 6, the irregular film 11 is specifically formed to almost the same film thickness in both the transparent region and the reflection region to provide substantially the same inter-substrate gap in these two regions so that they may have almost the same V-T characteristics and also the reflection electrode film 6 made of Al/Mo is formed so as to overlap with a transmission electrode film 5 made of ITO all around an outer periphery of the transmission electrode film 5 by a width of at least 2 ?m, thus suppressing electric erosion from occurring between the ITO and Al substances at the edge of the transmission electrode film 5.Type: GrantFiled: December 13, 2004Date of Patent: October 19, 2010Assignee: NEC LCD Technologies, Ltd.Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
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Patent number: 7075603Abstract: In a semi-transmission type liquid crystal display and a method for fabricating the same, a reflective electrode such as aluminum layer and a transparent electrode such as ITO film are used to form a pixel electrode that is provided on an organic film having an uneven surface. In order to effectively restrict the battery effect between a reflective electrode and a transparent electrode, a surface of the organic film is put in a plasma-processing and then is washed by a washing liquid. Thereafter, the transparent electrode is formed and then the reflective electrode such as a double layer electrode of the aluminum layer and the molybdenum layer are formed.Type: GrantFiled: October 29, 2002Date of Patent: July 11, 2006Assignee: NEC LCD Technologies, Ltd.Inventors: Satoshi Ihida, Masaki Shinohara, Manabu Oyama
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Patent number: 6972821Abstract: An active-matrix addressing LCD device that suppresses effectively the off leakage current induced by the charge-up of the spacers placed over the TFTs. The device comprises (a) a first substrate having switching elements; (b) a second substrate coupled with the first substrate in such a way as to form a gap with spacers between the first and second substrates; the spacers being distributed in the gap; (c) a liquid crystal confined in the gap; and (d) protrusions formed in overlapping areas with the switching elements; each of the protrusions being protruded in a direction that narrows the gap. The spacers distributed in the gap are likely to be shifted away from the overlapping areas due to the protrusions.Type: GrantFiled: May 13, 2002Date of Patent: December 6, 2005Assignee: NEC LCD Technologies, Ltd.Inventors: Kyounei Yasuda, Satoshi Ihida
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Patent number: 6917392Abstract: The present invention provides a liquid crystal display apparatus of a lateral direction electric field drive type comprising an array substrate including a plurality of TFTs each having a gate electrode, a gate insulation film, a semiconductor layer, and a source electrode/drain electrode formed on a transparent substrate and an opposing substrate arrange so as to oppose to the array substrate, wherein the semiconductor layer has a width in the gate length direction identical to the gate length.Type: GrantFiled: December 15, 2000Date of Patent: July 12, 2005Assignee: NEC LCD Technologies, Ltd.Inventors: Takahisa Hannuki, Shinichi Nishida, Satoshi Ihida, Shouichi Kuroha, Ryuji Takahashi, Satoshi Miura
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Patent number: 6891196Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer.Type: GrantFiled: July 11, 2003Date of Patent: May 10, 2005Assignee: NEC LCD Technologies, Ltd.Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
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Patent number: 6890783Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: GrantFiled: September 12, 2002Date of Patent: May 10, 2005Assignee: NEC LCD Technologies, LTD.Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20050094067Abstract: In a transflective type LCD provided with a transparent region and a reflection region in each pixel, when an irregular film 11 is formed on an active matrix substrate 12 to form irregularities of a reflection electrode film 6, the irregular film 11 is specifically formed to almost the same film thickness in both the transparent region and the reflection region to provide substantially the same inter-substrate gap in these two regions so that they may have almost the same V-T characteristics and also the reflection electrode film 6 made of Al/Mo is formed so as to overlap with a transmission electrode film 5 made of ITO all around an outer periphery of the transmission electrode film 5 by a width of at least 2 ?m, thus suppressing electric erosion from occurring between the ITO and Al substances at the edge of the transmission electrode film 5.Type: ApplicationFiled: December 13, 2004Publication date: May 5, 2005Applicants: NEC Corporation, NEC LCD Technologies, Ltd.Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
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Patent number: 6853421Abstract: In a transflective type LCD provided with a transparent region and a reflection region in each pixel, when an irregular film 11 is formed on an active matrix substrate 12 to form irregularities of a reflection electrode film 6, the irregular film 11 is specifically formed to almost the same film thickness in both the transparent region and the reflection region to provide substantially the same inter-substrate gap in these two regions so that they may have almost the same V-T characteristics and also the reflection electrode film 6 made of Al/Mo is formed so as to overlap with a transmission electrode film 5 made of ITO all around an outer periphery of the transmission electrode film 5 by a width of at least 2 ?m, thus suppressing electric erosion from occurring between the ITO and Al substances at the edge of the transmission electrode film 5.Type: GrantFiled: July 26, 2002Date of Patent: February 8, 2005Assignees: NEC Corporation, NEC LCD Technologies, Ltd.Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
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Patent number: 6788355Abstract: A method for fabricating an active matrix LCD panel for use in an active matrix LCD device includes the step of forming a passivation layer acting as a channel protection layer for protecting an amorphous silicon active layer, thereby reducing the number of photolithographic steps. A transparent conductive film is used for forming a gate electrode and a pixel electrode before formation of an amorphous silicon film for the TFTs.Type: GrantFiled: October 25, 2000Date of Patent: September 7, 2004Assignee: NEC LCD Technologies, Ltd.Inventors: Satoshi Ihida, Hirotaka Yamaguchi, Hiroaki Tanaka, Takasuke Hayase, Hiroshi Kanou, Wakahiko Kaneko, Tae Miyahara, Michiaki Sakamoto, Shinichi Nakata
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Patent number: 6759283Abstract: A method of fabricating a thin film transistor, includes the steps of (a) forming a gate electrode on an electrically insulating substrate, (b) forming a gate insulating film on the electrically insulating substrate, covering the gate electrode therewith, (c) forming a semiconductor layer on the gate insulating film above the gate electrode, (d) forming source and drain electrodes both making electrical contact with the semiconductor layer, (e) patterning the semiconductor layer into a channel, (f) applying first plasma to the semiconductor layer through the use of a first gas, and (g) applying second plasma to the semiconductor layer through the use of a second gas, and (h) forming an electrically insulating film covering the semiconductor layer therewith.Type: GrantFiled: May 15, 2002Date of Patent: July 6, 2004Assignee: NEC LCD Technologies, Ltd.Inventors: Kyounei Yasuda, Satoshi Ihida, Jukoh Funaki, Manabu Oyama, Yoshikazu Hatazawa