Abstract: A technique of performing anonymization without impairing usefulness of data. An anonymization apparatus includes an overlapping exclusion part configured to generate a partial table of M×L including L records of a table to be anonymized which have sets of values of p master attributes different from each other, from the table to be anonymized of M×N, where M is the number of attributes, N is the number of records, p is the number of master attributes, and L is the number of sets of values of p master attributes which are different from each other, an anonymization part configured to generate an anonymized partial table of M×L from the partial table by anonymizing the p master attributes in the partial table, and an overlapping restoration part configured to generate an anonymized table of M×N.

Abstract: The semiconductor circuit breaker includes a semiconductor switch unit connected to an AC circuit, and a phase control unit that controls conduction and non-conduction of the semiconductor switch unit by the control signal. The phase control unit includes an accident detection unit to detect an accident based on a current detected from the AC circuit, a zero point detection unit to detect a current zero point based on the current detected from the AC circuit, and a control signal output unit to output the control signal for setting the semiconductor switch unit to be non-conductive when the accident detection unit detects the accident or when the zero point detection unit detects the current zero point in response to a command to cut off the current.

Abstract: A communication control device included in a user plane of a mobile communication system in which a control plane and the user plane are separated includes: a packet transfer unit that transfers a packet to a network apparatus; a reception unit that receives, from the control plane, a basic DSCP being a DSCP set to each QoS flow by the control plane according to a QoS class; and a measurement unit that measures a use band amount of the packet for each of the QoS flow, and the packet transfer unit determines a new DSCP being a DSCP to be stored in the packet to be transferred, based on the basic DSCP and the use band amount of the QoS flow to which the packet to be transferred belongs, and stores the new DSCP in the packet to be transferred to the network apparatus.

Abstract: A washer pump configured to suck liquid stored in a tank and configured to jet the liquid to a surface to be cleaned. The washer pump includes: a housing attached to the tank, an impeller rotatably provided in the housing, a motor rotating the impeller, a motor accommodating portion provided in the housing and accommodating the motor, a corner portion provided in the housing and disposed between the motor accommodating portion and the tank, and a respiratory hole provided between the motor accommodating portion and the corner portion. The respiratory hole communicating an inside of the motor accommodating portion with an outside thereof.

Abstract: An identification unit analyzes a received packet and identifies a network slice to which the received packet belongs and a class in QoS. A group of queues includes a plurality of queue groups associated with the plurality of network slices. Each queue group includes a plurality of queues associated with a plurality of classes in the QoS. A distribution unit distributes the received packet to a queue according to an analysis result of the received packet. Each data transfer unit acquires the received packet from the queue associated with each class of the associated queue group, and performs packet transfer processing according to the QoS on the acquired received packet.

Abstract: Since the pump chamber (32a), the valve chambers (33a and 33b), the discharge holes (33e and 33f), and the flow paths (34 and 35) are integrally provided to each other in the housing (30), in the case where these are formed of separate members, a step or the like that inhibits the flow of the cleaning liquid “W” is not formed in the flow path of the cleaning liquid “W”, so that the pressure loss of the cleaning liquid “W” can be reduced. In addition, since the valve chambers (33a and 33b) of the flow paths (34 and 35) extend to the discharge holes (33e and 33f), the cleaning liquid “W” flowing out of the flow paths (34 and 35) can be discharged at a portion closer to the central of the valve chambers (33a and 33b). As a result, the outlet portions of the flow paths (34 and 35) and the inlet portions of the discharge holes (33e and 33f) is brought closer to each other, and the turbulent of the cleaning liquid “W” in the valve chambers (33a and 33b) can be suppressed, thereby reducing the pressure loss.

Abstract: A pump chamber (32a), valve chambers (33a and 33b), discharge holes (33e and 33f), and flow paths (34 and 35) are integrally provided to each other in a housing (30), so that the pressure loss of the cleaning liquid “W” can be reduced. In addition, since valve chambers of the flow paths extend to the discharge holes, the cleaning liquid flowing out of the flow paths can be discharged at a portion closer to the central of the valve chambers. As a result, the outlet portions of the flow paths and the inlet portions of the discharge holes is brought closer to each other, and the turbulent of the cleaning liquid in the valve chambers can be suppressed, thereby reducing the pressure loss.

Abstract: The semiconductor circuit breaker includes a semiconductor switch unit connected to an AC circuit, and a phase control unit that controls conduction and non-conduction of the semiconductor switch unit by the control signal. The phase control unit includes an accident detection unit to detect an accident based on a current detected from the AC circuit, a zero point detection unit to detect a current zero point based on the current detected from the AC circuit, and a control signal output unit to output the control signal for setting the semiconductor switch unit to be non-conductive when the accident detection unit detects the accident or when the zero point detection unit detects the current zero point in response to a command to cut off the current.

Abstract: Since the pump chamber (32a), the valve chambers (33a and 33b), the discharge holes (33e and 33f), and the flow paths (34 and 35) are integrally provided to each other in the housing (30), in the case where these are formed of separate members, a step or the like that inhibits the flow of the cleaning liquid “W” is not formed in the flow path of the cleaning liquid “W”, so that the pressure loss of the cleaning liquid “W” can be reduced. In addition, since the valve chambers (33a and 33b) of the flow paths (34 and 35) extend to the discharge holes (33e and 33f), the cleaning liquid “W” flowing out of the flow paths (34 and 35) can be discharged at a portion closer to the central of the valve chambers (33a and 33b). As a result, the outlet portions of the flow paths (34 and 35) and the inlet portions of the discharge holes (33e and 33f) is brought closer to each other, and the turbulent of the cleaning liquid “W” in the valve chambers (33a and 33b) can be suppressed, thereby reducing the pressure loss.

Abstract: A wiper blade includes a blade rubber and a rubber holder. In the rubber holder, a water channel through which a washing liquid flows along a longitudinal direction is provided. In the rubber holder, an injection port that communicates with the water channel and is configured to be opened by water pressure and inject the washing liquid is provided. The injection port is formed into a slit shape, and a plurality of injection ports are provided in the longitudinal direction. A width of the injection ports varies along the longitudinal direction, and the injection port closer to an outer end side has a larger slit width. A larger amount of the washing liquid is injected from the injection port having a larger slit width, and the injection amount of the washing liquid becomes larger toward the outer end side at which more washing liquid is required.

Abstract: A wiper blade includes a blade rubber and a rubber holder. In the rubber holder, a water channel through which a washing liquid flows along a longitudinal direction is provided. In the rubber holder, an injection port that communicates with the water channel and is configured to be opened by water pressure and inject the washing liquid is provided. The injection port is formed into a slit shape, and a plurality of injection ports are provided in the longitudinal direction. A width of the injection ports varies along the longitudinal direction, and the injection port closer to an outer end side has a larger slit width. A larger amount of the washing liquid is injected from the injection port having a larger slit width, and the injection amount of the washing liquid becomes larger toward the outer end side at which more washing liquid is required.

Abstract: A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.

Abstract: A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Abstract: A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Abstract: A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.