Patents by Inventor Satoshi KIYA
Satoshi KIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11812546Abstract: A high-frequency circuit includes a first dielectric layer, a circuit layer, a second dielectric layer arranged in this order, the circuit layer includes a transmission line of a high-frequency signal and a ground pattern disposed around the transmission line. An electromagnetic wave shield is disposed in the first dielectric layer and the second dielectric layer around the transmission line. The electromagnetic wave shield includes a first ground electric conductor formed on an inner surface of at least one first hole formed to extend through the first dielectric layer without extending through the ground pattern, and a second ground electric conductor formed on an inner surface of at least one second hole formed to extend through the second dielectric layer without extending through the ground pattern. The first ground electric conductor and the second ground electric conductor are each electrically connected to the ground pattern.Type: GrantFiled: May 10, 2021Date of Patent: November 7, 2023Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Nitta, Takafumi Uemiya, Suguru Yamagishi, Shigeki Shimada, Hiroshi Ueda, Satoshi Kiya
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Publication number: 20230232538Abstract: A substrate for a printed wiring board includes a base layer, and a copper foil directly or indirectly stacked on at least a part of one or both surfaces of the base layer. The base layer includes a matrix containing a fluororesin as a main component and one or more reinforcing material layers included in the matrix, and a ratio B/A is 0.003 to 0.37, where A is an average thickness of the base layer, and B is an average distance between a surface of the copper foil facing the matrix and a surface of a reinforcing material layer closest to the surface of the copper foil facing the copper foil.Type: ApplicationFiled: June 25, 2021Publication date: July 20, 2023Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Toshiki IWASAKI, Makoto NAKABAYASHI, Satoshi KIYA
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Publication number: 20230019563Abstract: A high-frequency circuit includes a first electric conductor layer, a first dielectric layer, a circuit layer, a second dielectric layer, a second electric conductor layer arranged in this order, and the circuit layer includes a ground pattern and a transmission line of a high-frequency signal. An electromagnetic wave shield is disposed around the transmission line. The electromagnetic wave shield includes a ground electric conductor on inner surfaces of a plurality of holes extending through the first dielectric layer, the ground pattern, the second dielectric layer, the first electric conductor layer, and the second electric conductor layer. The plurality of holes are a plurality of elongated holes provided at an interval in a direction in which the transmission line is surrounded. In each of the plurality of elongated holes, a longitudinal dimension in the direction in which the transmission line is surrounded is larger than a width dimension.Type: ApplicationFiled: May 10, 2021Publication date: January 19, 2023Applicants: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji NITTA, Takafumi UEMIYA, Suguru YAMAGISHI, Shigeki SHIMADA, Hiroshi UEDA, Satoshi KIYA
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Publication number: 20220418094Abstract: A high-frequency circuit includes a first dielectric layer, a circuit layer, a second dielectric layer arranged in this order, the circuit layer includes a transmission line of a high-frequency signal and a ground pattern disposed around the transmission line. An electromagnetic wave shield is disposed in the first dielectric layer and the second dielectric layer around the transmission line. The electromagnetic wave shield includes a first ground electric conductor formed on an inner surface of at least one first hole formed to extend through the first dielectric layer without extending through the ground pattern, and a second ground electric conductor formed on an inner surface of at least one second hole formed to extend through the second dielectric layer without extending through the ground pattern. The first ground electric conductor and the second ground electric conductor are each electrically connected to the ground pattern.Type: ApplicationFiled: May 10, 2021Publication date: December 29, 2022Applicants: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji NITTA, Takafumi UEMIYA, Suguru YAMAGISHI, Shigeki SHIMADA, Hiroshi UEDA, Satoshi KIYA
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Publication number: 20220272838Abstract: A method for manufacturing a dielectric sheet, includes the steps of extrusion molding a mixture including powder polytetrafluoroethylene and spherical silica at a temperature lower than or equal to a melting point of the polytetrafluoroethylene, and calendering a sheet body obtained by the extrusion molding. A mass ratio of the silica with respect to the polytetrafluoroethylene is 1.3 or greater. An average particle diameter of the silica is 0.1 ?m or greater but 3.0 ?m or less. A reduction ratio of the extrusion molding is 8 or less.Type: ApplicationFiled: May 11, 2021Publication date: August 25, 2022Inventors: Shingo KAIMORI, Takashi NINOMIYA, Motohiko SUGIURA, Yasuhiro OKUDA, Hideki KASHIHARA, Satoshi KIYA, Makoto NAKABAYASHI, Kentaro OKAMOTO, Chiaki TOKUDA
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Patent number: 11375615Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.Type: GrantFiled: August 6, 2016Date of Patent: June 28, 2022Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Printed Circuits, Inc., Sumitomo Electric Fine Polymer, Inc.Inventors: Yuichiro Yamanaka, Yoshio Oka, Satoshi Kiya, Yoshifumi Uchita, Makoto Nakabayashi
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Patent number: 11364714Abstract: A fluororesin base material containing a fluororesin as a main component includes a modified layer on at least a partial region of a surface thereof, the modified layer containing a siloxane bond and a hydrophilic organofunctional group, and a surface of the modified layer having a contact angle of 90° or less with pure water.Type: GrantFiled: October 8, 2014Date of Patent: June 21, 2022Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., Sumitomo Electric Industries, Ltd.Inventors: Satoshi Kiya, Sumito Uehara, Kousuke Miura, Makoto Nakabayashi
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Patent number: 10485102Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.Type: GrantFiled: June 20, 2018Date of Patent: November 19, 2019Assignees: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Shingo Kaimori, Masaaki Yamauchi, Kentaro Okamoto, Satoshi Kiya, Kazuo Murata
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Publication number: 20190215957Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.Type: ApplicationFiled: June 20, 2018Publication date: July 11, 2019Applicants: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Shingo KAIMORI, Masaaki YAMAUCHI, Kentaro OKAMOTO, Satoshi KIYA, Kazuo MURATA
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Publication number: 20180242450Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.Type: ApplicationFiled: August 6, 2016Publication date: August 23, 2018Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC FINE POLYMER, INC.Inventors: Yuichiro YAMANAKA, Yoshio OKA, Satoshi KIYA, Yoshifumi UCHITA, Makoto NAKABAYASHI
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Patent number: 9894765Abstract: An object of the present invention is to provide a printed wiring board in which conductive layers formed on two surfaces of a base layer that contains a fluororesin as a main component are reliably connected to each other through a via-hole. A printed wiring board according to an embodiment of the present invention includes a base layer containing a fluororesin as a main component, a first conductive layer stacked on one surface of the base layer, a second conductive layer stacked on the other surface of the base layer, and a via-hole that is formed along a connection hole penetrating the base layer and at least one of the first conductive layer and the second conductive layer in a thickness direction and that electrically connects the first conductive layer and the second conductive layer to each other. At least a part of an inner circumferential surface of the base layer in the connection hole has a pre-treated surface having a content ratio of oxygen atoms or nitrogen atoms of 0.2 atomic percent or more.Type: GrantFiled: May 12, 2015Date of Patent: February 13, 2018Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Kousuke Miura, Satoshi Kiya, Sumito Uehara
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Publication number: 20170327630Abstract: A resin film containing a fluororesin as a main component has, on at least one surface thereof, a pre-treated surface having a content ratio of oxygen atoms or nitrogen atoms of 0.2 atomic percent or more. A coverlay includes the resin film and an adhesive layer laminated on the pre-treated surface. A substrate for a printed wiring board includes the resin film and a conductive layer laminated on the pre-treated surface. A printed wiring board includes an insulating base layer, a conductive pattern laminated on at least one surface of the base layer, and the coverlay for a printed wiring board, the coverlay being laminated on the conductive pattern.Type: ApplicationFiled: October 13, 2015Publication date: November 16, 2017Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Satoshi KIYA, Sumito UEHARA, Kousuke MIURA
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Publication number: 20170118837Abstract: An object of the present invention is to provide a printed wiring board in which conductive layers formed on two surfaces of a base layer that contains a fluororesin as a main component are reliably connected to each other through a via-hole. A printed wiring board according to an embodiment of the present invention includes a base layer containing a fluororesin as a main component, a first conductive layer stacked on one surface of the base layer, a second conductive layer stacked on the other surface of the base layer, and a via-hole that is formed along a connection hole penetrating the base layer and at least one of the first conductive layer and the second conductive layer in a thickness direction and that electrically connects the first conductive layer and the second conductive layer to each other. At least a part of an inner circumferential surface of the base layer in the connection hole has a pre-treated surface having a content ratio of oxygen atoms or nitrogen atoms of 0.2 atomic percent or more.Type: ApplicationFiled: May 12, 2015Publication date: April 27, 2017Inventors: Kousuke MIURA, Satoshi KIYA, Sumito UEHARA
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Publication number: 20160250830Abstract: A fluororesin base material containing a fluororesin as a main component includes a modified layer on at least a partial region of a surface thereof, the modified layer containing a siloxane bond and a hydrophilic organofunctional group, and a surface of the modified layer having a contact angle of 90° or less with pure water.Type: ApplicationFiled: October 8, 2014Publication date: September 1, 2016Inventors: Satoshi KIYA, Sumito UEHARA, Kousuke MIURA, Makoto NAKABAYASHI
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Patent number: RE49929Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.Type: GrantFiled: November 17, 2021Date of Patent: April 16, 2024Assignees: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Shingo Kaimori, Masaaki Yamauchi, Kentaro Okamoto, Satoshi Kiya, Kazuo Murata