Patents by Inventor Satoshi KONAGAI
Satoshi KONAGAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121797Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.Type: GrantFiled: September 19, 2016Date of Patent: November 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigeki Kobayashi, Satoshi Konagai, Atsushi Konno, Kenta Yamada, Masaaki Higuchi, Masao Shingu, Soichiro Kitazaki, Yoshimasa Mikajiri
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Patent number: 9935121Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.Type: GrantFiled: March 8, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Konagai, Yoshihiro Akutsu, Masaru Kito
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Publication number: 20180076216Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar member, and an insulating film. The stacked body is provided on the substrate, and includes a plurality of electrode layers separately stacked each other. The columnar member is provided in the stacked body, and includes a first semiconductor portion extending in a stacked direction of the plurality of electrode layers. The insulating film covers a bottom portion of the columnar member.Type: ApplicationFiled: March 20, 2017Publication date: March 15, 2018Applicant: Toshiba Memory CorporationInventor: Satoshi KONAGAI
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Patent number: 9917101Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar member, and an insulating film. The stacked body is provided on the substrate, and includes a plurality of electrode layers separately stacked each other. The columnar member is provided in the stacked body, and includes a first semiconductor portion extending in a stacked direction of the plurality of electrode layers. The insulating film covers a bottom portion of the columnar member.Type: GrantFiled: March 20, 2017Date of Patent: March 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Satoshi Konagai
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Patent number: 9876028Abstract: The memory string comprises: a plurality of control gate electrodes stacked on the substrate and extending in a first direction and a second direction parallel to the substrate; a semiconductor layer that has one end thereof connected to the substrate, has as its longitudinal direction a third direction perpendicular to the substrate, and faces the plurality of control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the semiconductor layer. The contact includes, in the third direction, a first portion, a second portion which is more to a substrate side than is the first portion, and a third portion which is more to the substrate side than is the second portion. A width of the second portion is larger than a width of the first portion, and larger than a width of the third portion.Type: GrantFiled: September 15, 2016Date of Patent: January 23, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Satoshi Konagai
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Publication number: 20170243873Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.Type: ApplicationFiled: September 19, 2016Publication date: August 24, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki KOBAYASHI, Satoshi KONAGAI, Atsushi KONNO, Kenta YAMADA, Masaaki HIGUCHI, Masao SHINGU, Soichiro KITAZAKI, Yoshimasa MIKAJIRI
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Publication number: 20170196859Abstract: [Problem] Provided is a pharmaceutical composition for treating cancer in which one or more kinases of BTK, JAK3, and ITK is involved. [Means for Solution] The present inventors studied compounds having a BTK inhibiting effect, a JAK3 inhibiting effect and an ITK inhibiting effect, and confirmed that a specific pyrazine carboxamide compound has the BTK inhibiting effect, the JAK3 inhibiting effect, and the ITK inhibiting effect, and that a pharmaceutical composition comprising the compound as an active ingredient has a therapeutic effect on cancer in which one or more kinases of BTK, JAK3 and ITK is involved, in another aspect, cancer in which BTK is overexpressed or activated, in another aspect, cancer in which a B cell receptor signal is activated, in still another aspect, cancer in which JAK3 is activation-mutated or activated, and in still another aspect, cancer in which ITK is activated, thereby completing the present invention.Type: ApplicationFiled: May 27, 2015Publication date: July 13, 2017Applicant: Astellas Pharma Inc.Inventors: Satoshi KONAGAI, Hiroaki TANAKA, Hiroko YAMAMOTO, Hideki SAKAGAMI
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Publication number: 20170200735Abstract: The memory string comprises: a plurality of control gate electrodes stacked on the substrate and extending in a first direction and a second direction parallel to the substrate; a semiconductor layer that has one end thereof connected to the substrate, has as its longitudinal direction a third direction perpendicular to the substrate, and faces the plurality of control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the semiconductor layer. The contact includes, in the third direction, a first portion, a second portion which is more to a substrate side than is the first portion, and a third portion which is more to the substrate side than is the second portion. A width of the second portion is larger than a width of the first portion, and larger than a width of the third portion.Type: ApplicationFiled: September 15, 2016Publication date: July 13, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Satoshi KONAGAI
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Patent number: 9673215Abstract: According to one embodiment, the metal oxide films are provided between the metal layers and the insulating layers. The first metal nitride films are provided between the metal oxide films and the metal layers. The second metal nitride films are provided between the first metal nitride films and the metal layers. The intermediate films are provided between the first metal nitride films and the second metal nitride films. The intermediate films are of a different type of material from the metal oxide films.Type: GrantFiled: July 5, 2016Date of Patent: June 6, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Konagai, Shigeki Kobayashi
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Publication number: 20170077131Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.Type: ApplicationFiled: March 8, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi KONAGAI, Yoshihiro Akutsu, Masaru Kito
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Patent number: 9053783Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a first line is disposed on a semiconductor substrate. A first memory cell is disposed on a side opposite to the semiconductor substrate with respect to the first line. A second line intersects with the first line via the first memory cell. A second memory cell is disposed on a side opposite to the semiconductor substrate with respect to the second line. A third line intersects with the second line via the second memory cell. The first memory cell has a first resistance change layer and a first rectification layer. The second memory cell has a second resistance change layer and a second rectification layer. A composition of the first resistance change layer is different from a composition of the second resistance change layer.Type: GrantFiled: March 16, 2012Date of Patent: June 9, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Satoshi Konagai
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Patent number: 9042158Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.Type: GrantFiled: September 11, 2013Date of Patent: May 26, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoichi Minemura, Takayuki Tsukamoto, Takamasa Okawa, Hiroshi Kanno, Atsushi Yoshida, Satoshi Konagai, Nobuaki Yasutake
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Publication number: 20140347911Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.Type: ApplicationFiled: September 11, 2013Publication date: November 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoichi Minemura, Takayuki Tsukamoto, Takamasa Okawa, Hiroshi Kanno, Atsushi Yoshida, Satoshi Konagai, Nobuaki Yasutake
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Publication number: 20130197009Abstract: [Problem] An object of the present invention is to provide a novel anticancer drug which is useful for treating prostate cancer accompanying androgen receptor mutation [Means for Solution] The present inventors conducted thorough research on mutant androgen-related diseases for which the traditional anti-androgen drugs become ineffective. As a result, they found that the compound, which is an active ingredient of the pharmaceutical composition of the present invention, exhibits an inhibitory action against transcriptional activation in a human mutant androgen receptor (AR), and has an excellent antitumor action in a human prostate cancer-bearing mouse, thereby completing the present invention. Accordingly, the compound, which is an active ingredient of the pharmaceutical composition of the present invention, is useful for a series of androgen receptor-related diseases including prostate cancer.Type: ApplicationFiled: October 21, 2011Publication date: August 1, 2013Applicant: ASTELLAS PHARMA INC.Inventors: Yukitaka Ideyama, Sadao Kuromitsu, Takashi Furutani, Masayoshi Takeda, Satoshi Konagai, Tomohiro Yamada, Nobuaki Taniguchi, Yutaka Kondoh, Masaaki Hirano, Kazushi Watanabe, Takashi Sugane, Akio Kakefuda
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Publication number: 20120241716Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a first line is disposed on a semiconductor substrate. A first memory cell is disposed on a side opposite to the semiconductor substrate with respect to the first line. A second line intersects with the first line via the first memory cell. A second memory cell is disposed on a side opposite to the semiconductor substrate with respect to the second line. A third line intersects with the second line via the second memory cell. The first memory cell has a first resistance change layer and a first rectification layer. The second memory cell has a second resistance change layer and a second rectification layer. A composition of the first resistance change layer is different from a composition of the second resistance change layer.Type: ApplicationFiled: March 16, 2012Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Satoshi KONAGAI