Patents by Inventor Satoshi Makioka
Satoshi Makioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8745569Abstract: Provided is a simulation method for simulating electrical properties of a bidirectional switch formed as a single element and having a double gate structure. A simulation is performed using an equivalent circuit having a symmetrical structure in which a drain electrode of a JFET and a drain electrode of another JFET are connected via a resistor.Type: GrantFiled: April 22, 2013Date of Patent: June 3, 2014Assignee: Panasonic CorporationInventors: Hiroaki Ueno, Satoshi Makioka, Manabu Yanagihara
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Publication number: 20130232462Abstract: Provided is a simulation method for simulating electrical properties of a bidirectional switch formed as a single element and having a double gate structure. A simulation is performed using an equivalent circuit having a symmetrical structure in which a drain electrode of a JFET and a drain electrode of another JFET are connected via a resistor.Type: ApplicationFiled: April 22, 2013Publication date: September 5, 2013Applicant: Panasonic CorporationInventors: Hiroaki UENO, Satoshi MAKIOKA, Manabu YANAGIHARA
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Patent number: 8013673Abstract: An RF power amplifier according to an implementation of the present invention includes: a first power amplifier which linearly amplifies a first RF signal of a first frequency band; a second power amplifier which linearly amplifies a second RF signal of a second frequency band lower than the first frequency band; a third power amplifier which nonlinearly amplifies a third RF signal of the first frequency band; a fourth power amplifier which nonlinearly amplifies a fourth RF signal of the second frequency band, and input lines of the respective power amplifiers do not cross each other on semiconductor substrates, and the output lines of the respective power amplifiers do not cross each other on the semiconductor substrates.Type: GrantFiled: August 20, 2010Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Satoshi Makioka, Masahiko Inamori, Motoyoshi Iwata
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Publication number: 20110057730Abstract: To provide a multiband RF power amplifier which operates with improved isolation at multiple bands and in multiple modes in each of the bands. An RF power amplifier according to an implementation of the present invention includes a first power amplifying circuit, a second power amplifying circuit, a third power amplifying circuit, and a fourth power amplifying circuit, and the first to the fourth power amplifying circuits each include, on a semiconductor substrate, an input pad for wire bonding, an input line, a power amplifier, an output line, and an output pad, and such input lines do not cross each other on chips, and such output lines do not cross each other on the chips.Type: ApplicationFiled: September 1, 2010Publication date: March 10, 2011Applicant: PANASONIC CORPORATIONInventors: Satoshi MAKIOKA, Masahiko INAMORI
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Publication number: 20110050348Abstract: An RF power amplifier according to an implementation of the present invention includes: a first power amplifier which linearly amplifies a first RF signal of a first frequency band; a second power amplifier which linearly amplifies a second RF signal of a second frequency band lower than the first frequency band; a third power amplifier which nonlinearly amplifies a third RF signal of the first frequency band; a fourth power amplifier which nonlinearly amplifies a fourth RF signal of the second frequency band, and input lines of the respective power amplifiers do not cross each other on semiconductor substrates, and the output lines of the respective power amplifiers do not cross each other on the semiconductor substrates.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: PANASONIC CORPORATIONInventors: Satoshi MAKIOKA, Masahiko INAMORI, Motoyoshi IWATA
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Patent number: 7227418Abstract: In order to supply a bias voltage to the base terminals of heterojunction bipolar transistors (HBTs) Q1 to Q3 connected in parallel to one another, resistors RB1 to RB3 and heterojunction bipolar transistors QB1 to QB3 whose base terminals are connected to the collector terminal thereof are provided. The amplifier transistors Q1 to Q3 have the same temperature characteristics as those of the bias-producing transistors QB1 to QB3. With the bias circuit, it is possible to compensate for the temperature characteristics of the amplifier transistors Q1 to Q3. Since the resistance values of the resistors RB1 to RB3 can be decreased, it is possible to suppress the decrease in the output power and to prevent the occurrence of the collapse phenomenon. Thus, it is possible to obtain a power amplifier capable of preventing the thermal runaway and compensating for the temperature characteristics without deteriorating the output characteristics.Type: GrantFiled: January 21, 2005Date of Patent: June 5, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Satoshi Makioka
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Publication number: 20050218990Abstract: In order to supply a bias voltage to the base terminals of heterojunction bipolar transistors (HBTs) Q1 to Q3 connected in parallel to one another, resistors RB1 to RB3 and heterojunction bipolar transistors QB1 to QB3 whose base terminals are connected to the collector terminal thereof are provided. The amplifier transistors Q1 to Q3 have the same temperature characteristics as those of the bias-producing transistors QB1 to QB3. With the bias circuit, it is possible to compensate for the temperature characteristics of the amplifier transistors Q1 to Q3. Since the resistance values of the resistors RB1 to RB3 can be decreased, it is possible to suppress the decrease in the output power and to prevent the occurrence of the collapse phenomenon. Thus, it is possible to obtain a power amplifier capable of preventing the thermal runaway and compensating for the temperature characteristics without deteriorating the output characteristics.Type: ApplicationFiled: January 21, 2005Publication date: October 6, 2005Inventor: Satoshi Makioka
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Publication number: 20050189611Abstract: An insulator layer is fabricated that is composed of a large number of insulating ridges formed with predetermined mutual spacing on a Si substrate. Then, an inductor conductor layer is formed in a spiral or swirl pattern on the insulator layer. An outgoing wiring conductor layer is provided between the Si substrate and the insulator layer, while a via hole is provided in the insulator layer immediately under the center-side end portion of the spiral or swirl of the inductor conductor layer, so that the center-side end portion of the spiral or swirl of the inductor conductor layer is connected to the outgoing wiring conductor layer through the via hole.Type: ApplicationFiled: January 13, 2005Publication date: September 1, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Satoshi Makioka
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Patent number: 5796165Abstract: A multilayer structure composed of a plurality of substrates stacked in layers is provided with a cavity formed by partially removing some of the substrates. A semiconductor chip internally provided with an active component such as an FET is mounted on the bottom face of the cavity. Passive components including a high-frequency matching circuit and a bias circuit are distributed in the uppermost layer, lowermost layer, and middle layer lying between the substrates of the multilayer structure. For example, a chip component partially composing the high-frequency matching circuit is disposed in the uppermost layer, while the bias circuit is disposed in the middle layer. Since only a reduced number of substrates underlie the semiconductor chip internally provided with the active component primarily serving as a heating element, an excellent heat dissipating ability is retained even when each of the substrates of the multilayer structure is composed of a versatile material such as alumina.Type: GrantFiled: April 26, 1996Date of Patent: August 18, 1998Assignee: Matsushita Electronics CorporationInventors: Noriyuki Yoshikawa, Kunihiko Kanazawa, Satoshi Makioka, Kazuki Tateoka