Patents by Inventor Satoshi Mitsugi

Satoshi Mitsugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11815348
    Abstract: According to one embodiment, a template includes an alignment mark. The alignment mark includes first marks arranged at a first pitch in a first direction and second marks arranged at a second pitch in the first direction. At least one of the first marks includes a first region and a third region. At least one of the second marks includes a second region and the third region. The first region has first patterns arranged in a line-and-space form in the first direction. The second region has second patterns arranged in a line-and-space form in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Takashi Sato, Satoshi Mitsugi
  • Publication number: 20230298888
    Abstract: According to one embodiment, a pattern forming method includes forming a first resin pattern on a substrate with a first resin. The first resin pattern includes a first transfer pattern and a first mark. A second resin is dispensed to cover the first mark of the first resin pattern. A first pattern is formed including the first transfer pattern and the second resin covering the first mark. The first pattern is then transferred to a first process film on the substrate.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 21, 2023
    Inventor: Satoshi MITSUGI
  • Publication number: 20220307826
    Abstract: According to one embodiment, a template includes an alignment mark. The alignment mark includes first marks arranged at a first pitch in a first direction and second marks arranged at a second pitch in the first direction. At least one of the first marks includes a first region and a third region. At least one of the second marks includes a second region and the third region. The first region has first patterns arranged in a line-and-space form in the first direction. The second region has second patterns arranged in a line-and-space form in a second direction orthogonal to the first direction.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 29, 2022
    Applicant: Kioxia Corporation
    Inventors: Takashi SATO, Satoshi Mitsugi
  • Publication number: 20220308440
    Abstract: A template of one embodiment includes an alignment mark. The alignment mark includes a first main pattern and a first auxiliary pattern. In the first main pattern, a first part and a second part are disposed according to a predetermined repeating pattern. The first auxiliary pattern is configured as a pattern opposite to the repeating pattern in a region outside an end of the first main pattern.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 29, 2022
    Applicant: Kioxia Corporation
    Inventors: Takashi SATO, Takeshi SUTO, Satoshi MITSUGI
  • Patent number: 10908519
    Abstract: In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Satoshi Mitsugi
  • Publication number: 20200301293
    Abstract: In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.
    Type: Application
    Filed: September 11, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Satoshi MITSUGI
  • Patent number: 10739676
    Abstract: In an alignment mark of an embodiment, a first pattern has a periodic structure in a first direction on a surface of an original or a surface of a substrate and extends in a second direction, and a second pattern has a periodic structure in a third direction on the surface of the original or the surface of the substrate and extends in a fourth direction. The first direction and the third direction are parallel to each other. A period in the first direction of the periodic structure of the first pattern is equal to a period in the third direction of the periodic structure of the second pattern. At least one of the first pattern and the second pattern has a periodic structure in a fifth direction orthogonal to the first direction and the third direction on the surface of the original or the surface of the substrate. At least one of the second direction and the fourth direction is oblique with respect to the fifth direction.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Satoshi Mitsugi
  • Publication number: 20190369488
    Abstract: In an alignment mark of an embodiment, a first pattern has a periodic structure in a first direction on a surface of an original or a surface of a substrate and extends in a second direction, and a second pattern has a periodic structure in a third direction on the surface of the original or the surface of the substrate and extends in a fourth direction. The first direction and the third direction are parallel to each other. A period in the first direction of the periodic structure of the first pattern is equal to a period in the third direction of the periodic structure of the second pattern. At least one of the first pattern and the second pattern has a periodic structure in a fifth direction orthogonal to the first direction and the third direction on the surface of the original or the surface of the substrate. At least one of the second direction and the fourth direction is oblique with respect to the fifth direction.
    Type: Application
    Filed: March 12, 2019
    Publication date: December 5, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Satoshi Mitsugi
  • Patent number: 10290498
    Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Mitsugi, Takeshi Suto, Takashi Sato, Yukiyasu Arisawa
  • Publication number: 20190080899
    Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi MITSUGI, Takeshi SUTO, Takashi SATO, Yukiyasu ARISAWA
  • Patent number: 9472712
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Mitsugi, Hiroshi Katsuno
  • Publication number: 20160211408
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.
    Type: Application
    Filed: September 3, 2015
    Publication date: July 21, 2016
    Inventors: Satoshi Mitsugi, Hiroshi Katsuno
  • Patent number: 9368682
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 14, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 9337385
    Abstract: A semiconductor light emitting element includes a substrate and a stacked body. The stacked body is aligned with the substrate. The stacked body includes first and second semiconductor layers, a light emitting layer, and first and second electrodes. The first semiconductor layer has a first face including first and second portions. The first portion is provided with a plurality of convex portions. The second portion is aligned with the first portion. The second semiconductor layer is provided facing the second portion. The light emitting layer is provided between the second portion and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the light emitting layer. An interval of each of the convex portions is no less than 0.5 times and no more than 4 times a wavelength of a light emitted from the light emitting layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Mitsugi, Shinji Yamada, Shinya Nunoue
  • Patent number: 9337396
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first metal layer, a second metal layer, a third metal layer, a semiconductor light emitting unit and an insulating unit. The semiconductor light emitting unit is separated from the first metal layer in a first direction. The second metal layer is provided between the first metal layer and the semiconductor light emitting unit to be electrically connected to the first metal layer, and is light-reflective. The second metal layer includes a contact metal portion, and a peripheral metal portion. The third metal layer is light-reflective. The third metal layer includes an inner portion, a middle portion, and an outer portion. The insulating unit includes an first insulating portion, a second insulating portion, and a third insulating portion.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshihide Ito, Shinya Nunoue
  • Patent number: 9324917
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Satoshi Mitsugi, Shinya Nunoue
  • Patent number: 9311606
    Abstract: According to one embodiment, a quantum computer includes a crystal, an optical resonator, and a light source. A host crystal included in the crystal satisfying three conditions a first condition that maximum phonon energy of the host crystal is low, and so that a homogenous broadening of a 3F3(1) level of the Pr3+ ion resulting from relaxation due to phonon emission is smaller than respective hyperfine splits of a 3H4(1) level and the 3F3(1) level of the Pr3+ ion, a second condition that a site of the Pr3+ ion does not have inversion symmetry, and the Pr3+ ion has a Stark level in which the 3H4(1) level and the 3F3(1) level of the Pr3+ ion are not degenerate, and a third condition that each atom in the host crystal has no electronic magnetic moment.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato Goto, Satoshi Mitsugi, Kouichi Ichimura
  • Patent number: 9299889
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: March 29, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 9299903
    Abstract: According to one embodiment, a semiconductor light emitting element includes a semiconductor layer, a first conductive layer, and a second conductive layer. The second conductive layer is provided between the semiconductor layer and the first conductive layer. A light transmittance of the second conductive layer is higher than a light transmittance of the first conductive layer. An extinction coefficient of the second conductive layer is 0.005 or less.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 29, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Mitsugi, Toshihide Ito
  • Patent number: 9299901
    Abstract: According to one embodiment, a semiconductor light emitting device includes a metal layer, a stacked structural body, a first electrode, a pad electrode, a first conductive layer, a second conductive layer and an insulating layer. The metal layer includes a major surface having a first region, a second region, a third region and a fourth region. The stacked structural body includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The first semiconductor layer includes a first portion and a second portion. The second semiconductor layer is provided between the first region and the first portion. The first electrode is provided between the second region and the second portion. The pad electrode is provided on the third region. The first conductive layer is provided between the second region and the first electrode and between the third region and the pad electrode.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 29, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshihide Ito, Shinya Nunoue