Abstract: A wiring substrate includes a first wiring layer on a surface of a first insulating layer; a via interconnect including a first portion connected to the first wiring layer and a second portion formed monolithically with the first portion and extending from an end of the first portion in a direction away from the first wiring layer; a second insulating layer on the first insulating layer; and a second wiring layer on the second insulating layer, contacting a first surface of the second portion. The area of a cross section of the first portion, parallel to the surface of the first insulating layer, increases as the position of the cross section approaches the first wiring layer from the second portion. The second portion includes a second surface that is opposite from its first surface and extends horizontally from the end of the first portion to overhang the first portion.

Abstract: A wiring substrate includes a first wiring layer on a surface of a first insulating layer; a via interconnect including a first portion connected to the first wiring layer and a second portion formed monolithically with the first portion and extending from an end of the first portion in a direction away from the first wiring layer; a second insulating layer on the first insulating layer; and a second wiring layer on the second insulating layer, contacting a first surface of the second portion. The area of a cross section of the first portion, parallel to the surface of the first insulating layer, increases as the position of the cross section approaches the first wiring layer from the second portion. The second portion includes a second surface that is opposite from its first surface and extends horizontally from the end of the first portion to overhang the first portion.

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract: A wiring substrate includes a wiring pattern, which includes an upper surface forming a desired recognition mark, and a solder resist layer, which covers the wiring pattern. The solder resist layer includes a recess that entirely exposes the upper surface of the wiring pattern. The solder resist layer includes a solder resist layer formed at a region corresponding to the recess and a solder resist layer formed outside the recess. The recess entirely exposes the upper surface of the wiring pattern as the recognition mark, and the solder resist layer is formed at portions outside the upper surface of the wiring pattern.

Abstract: A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.

Abstract: A wiring substrate includes a wiring pattern, which includes an upper surface forming a desired recognition mark, and a solder resist layer, which covers the wiring pattern. The solder resist layer includes a recess that entirely exposes the upper surface of the wiring pattern. The solder resist layer includes a solder resist layer formed at a region corresponding to the recess and a solder resist layer formed outside the recess. The recess entirely exposes the upper surface of the wiring pattern as the recognition mark, and the solder resist layer is formed at portions outside the upper surface of the wiring pattern.

Abstract: A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.

Abstract: In a circuit analyzing method, coordinate points of nodes in an analysis target circuit are detected from layout data of the analysis target circuit to store in a storage unit, and a minimum area from among areas is specified by referring to a storage unit to read out the coordinate points of the nodes and by defining the areas containing all the nodes based on the read coordinate points of the nodes. A distance parameter prescribing a size of the minimum area is calculated, a variation coefficient is specified by using the distance parameter. Thus, a delay time in the analysis target circuit is calculated by using the variation coefficient.