Patents by Inventor Satoshi Tatsukawa

Satoshi Tatsukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11298908
    Abstract: A lid forming device of a cardboard box using a first flap with a slit and a second flap to be extended after being bent into a mountain shape is disclosed. The lid forming device includes first and second folding mechanisms. The fist folding mechanism folds the first flap in a direction of closing the opening. The second folding mechanism bends the second flap into a mountain shape and inserts part of the second flap into the slit of the first flap while extending the second flap. The second folding mechanism includes first and second retaining units. The first retaining unit retains a first face of the second flap located between a free end of the second flap and a bend line set beforehand in the second flap. The second retaining unit retains a second face of the second flap located between an anchored end and the bend line.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 12, 2022
    Assignee: ISHIDA CO., LTD.
    Inventors: Yuichi Nakamura, Tatsuya Iwasa, Atsushi Takahashi, Satoshi Tatsukawa, Satoshi Nishitsuji, Tatsuya Arimatsu, Koji Ono
  • Publication number: 20210101354
    Abstract: A cardboard box assembly device, that folds four flaps provided at edges of an opening in a cardboard box to surround the opening, is disclosed. The cardboard box assembly device includes a folding unit, a pushing unit, and a drive unit. The folding unit folds each of the four flaps in a prescribed sequence and closes the opening. The pushing unit pushes one of the four flaps, that is folded last, inward into the cardboard box as a locking flap, and overlaps the locking flap onto the other flaps. The drive unit contacts the cardboard box and imparts a prescribed displacement to the cardboard box. Parts that engage with one another are formed between the locking flap and at least one of the other flaps. The drive unit moves the locking flap relative to the other flaps due to the displacement when the pushing unit pushes the locking flap.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 8, 2021
    Inventors: Tatsuya IWASA, Satoshi NISHITSUJI, Tatsuya ARIMATSU, Satoshi TATSUKAWA
  • Patent number: 10960997
    Abstract: A case sealing device is disclosed. The case sealing device conveys a cardboard box and simultaneously closes a flap group provided on edges of opening of the cardboard box. The case sealing device includes a folding member, a drive unit, and a control unit. The folding member contacts a flap of the flap group that extends along a conveyance direction of the cardboard box and folds the flap. The drive unit moves the folding member. The control unit controls the drive unit. In operation of folding the flap, a longitudinal direction of the folding member is inclined with respect to the conveyance direction such that the folding member contacts a front edge of the flap in the conveyance direction before other portions of the flap.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 30, 2021
    Assignee: ISHIDA CO., LTD.
    Inventor: Satoshi Tatsukawa
  • Publication number: 20200254708
    Abstract: A lid forming device of a cardboard box using a first flap with a slit and a second flap to be extended after being bent into a mountain shape is disclosed. The lid forming device includes first and second folding mechanisms. The fist folding mechanism folds the first flap in a direction of closing the opening. The second folding mechanism bends the second flap into a mountain shape and inserts part of the second flap into the slit of the first flap while extending the second flap. The second folding mechanism includes first and second retaining units. The first retaining unit retains a first face of the second flap located between a free end of the second flap and a bend line set beforehand in the second flap. The second retaining unit retains a second face of the second flap located between an anchored end and the bend line.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 13, 2020
    Inventors: Yuichi NAKAMURA, Tatsuya IWASA, Atsushi TAKAHASHI, Satoshi TATSUKAWA, Satoshi NISHITSUJI, Tatsuya ARIMATSU, Koji ONO
  • Publication number: 20190263547
    Abstract: A case sealing device is disclosed. The case sealing device conveys a cardboard box and simultaneously closes a flap group provided on edges of opening of the cardboard box. The case sealing device includes a folding member, a drive unit, and a control unit. The folding member contacts a flap of the flap group that extends along a conveyance direction of the cardboard box and folds the flap. The drive unit moves the folding member. The control unit controls the drive unit. In operation of folding the flap, a longitudinal direction of the folding member is inclined with respect to the conveyance direction such that the folding member contacts a front edge of the flap in the conveyance direction before other portions of the flap.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventor: Satoshi TATSUKAWA
  • Patent number: 9143714
    Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Nishikido, Yasutoshi Aibara, Hirokazu Shimizu, Satoshi Tatsukawa, Takayoshi Shigekura
  • Publication number: 20140152879
    Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.
    Type: Application
    Filed: February 6, 2014
    Publication date: June 5, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Osamu NISHIKIDO, Yasutoshi Aibara, Hirokazu Shimizu, Satoshi Tatsukawa, Takayoshi Shigekura
  • Patent number: 8681032
    Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Nishikido, Yasutoshi Aibara, Hirokazu Shimizu, Satoshi Tatsukawa, Takayoshi Shigekura
  • Patent number: 6529418
    Abstract: A normal array for storing data in a non-volatile manner is divided into m sectors each corresponding to a unit subjected to a single data write or erase operation (where m is a natural number). An extra memory array includes a plurality of extra sectors each corresponding to a unit subjected to a single data read operation. The number of extra sectors is equal to or smaller than m. Each extra sector stores the data of the data write conditions or erase conditions corresponding to one of the m sectors in a non-volatile manner. The data write operation or erase operation is conducted based on the information corresponding to a selected sector, which is read from the extra memory array.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroaki Nakai, Satoshi Tatsukawa, Kei Maejima
  • Publication number: 20020141236
    Abstract: A normal array for storing data in a non-volatile manner is divided into m sectors each corresponding to a unit subjected to a single data write or erase operation (where m is a natural number). An extra memory array includes a plurality of extra sectors each corresponding to a unit subjected to a single data read operation. The number of extra sectors is equal to or smaller than m. Each extra sector stores the data of the data write conditions or erase conditions corresponding to one of the m sectors in a non-volatile manner. The data write operation or erase operation is conducted based on the information corresponding to a selected sector, which is read from the extra memory array.
    Type: Application
    Filed: September 24, 2001
    Publication date: October 3, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroaki Nakai, Satoshi Tatsukawa, Kei Maejima
  • Patent number: 6380636
    Abstract: In a memory cell array having sub-bit lines and sub-source lines formed of a diffusion layer, a main bit line is arranged commonly to the sub-bit lines arranged in multiple columns. A memory cell area can be reduced without restrictions by pitch conditions of the main bit lines.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: April 30, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Tatsukawa, Yuichi Kunori, Satoru Tamada