Patents by Inventor Satoshi Yamakawa

Satoshi Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6600198
    Abstract: A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit including an MOS transistor for cutting off conduction when a difference in voltage between electric signals sent between the terminals is smaller in absolute value than a threshold voltage of the MOS transistor, and conducts when the absolute value is at least equal to the threshold voltage.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: July 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahiro Ohnakado, Satoshi Yamakawa
  • Publication number: 20030097454
    Abstract: A switch device has an object ID rewrite unit and a file access control unit. The object ID rewrite unit, when an original object ID is contained in a reply to be transferred, rewrites the original object ID to an information entraining object ID by inserting server identification information into the original object ID, while when the information entraining object ID is contained in a reply to be transferred, restores the information entraining object ID to the original object ID. The file access control unit includes a table for managing a combination of address information of a server and server identification information, estimating address information of a server corresponding to sever identification information contained in an information entraining object of a request to be transferred with reference to the table, and determines a destination of the request on the basis of the address information.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 22, 2003
    Applicant: NEC CORPORATION
    Inventors: Satoshi Yamakawa, Jun Ishikawa, Takashi Torii
  • Patent number: 6465851
    Abstract: Epitaxial silicon layers are formed on n+-source/drain regions of two MOS transistors neighboring to each other and formed on a silicon substrate, respectively. In this processing, polycrystalline silicon pieces are generated on an element isolating and insulating film and others. Thereafter, the silicon substrate is exposed to an oxygen atmosphere so that hydrogen reacts with silicon at the surfaces of the epitaxial silicon layers and the surfaces of the polycrystalline silicon pieces to form silicon oxide films and polycrystalline silicon pieces. Thereby, short-circuit between MOS transistors in neighboring memory cells is prevented, and a semiconductor device has a high electrical reliability.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 15, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Satoshi Yamakawa, Yuji Abe
  • Patent number: 6465316
    Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: October 15, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuyoshi Hattori, Satoshi Yamakawa, Junji Nakanishi
  • Publication number: 20020146878
    Abstract: A semiconductor device causing no malfunction and having high ESD resistance against all cases of surges as well as a method of manufacturing the same are obtained.
    Type: Application
    Filed: September 6, 2001
    Publication date: October 10, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahiro Ohnakado, Satoshi Yamakawa
  • Publication number: 20020140019
    Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.
    Type: Application
    Filed: May 13, 2002
    Publication date: October 3, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Satoshi Yamakawa, Yoshihiko Toyoda
  • Patent number: 6417534
    Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: July 9, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Satoshi Yamakawa, Yoshihiko Toyoda
  • Patent number: 6373108
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno
  • Patent number: 6372593
    Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushika Kaisha
    Inventors: Nobuyoshi Hattori, Satoshi Yamakawa, Junji Nakanishi
  • Publication number: 20020019105
    Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
    Type: Application
    Filed: October 15, 2001
    Publication date: February 14, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Nobuyoshi Hattori, Satoshi Yamakawa, Junji Nakanishi
  • Publication number: 20020013940
    Abstract: A content rental system is disclosed, that comprises a content producer for producing a content, a rental business server, disposed in a store managed by a rental business operator, for recording the content produced by the content producer and downloading the content to a record medium corresponding to a command issued by a customer, and a reproducing device, disposed in the house of the customer, for reproducing the content from the record medium.
    Type: Application
    Filed: May 9, 2001
    Publication date: January 31, 2002
    Inventors: Yuji Tsukamoto, Takahiko Tsujisawa, Jun Ishikawa, Yasushi Kikkawa, Katsuaki Yamamoto, Satoshi Yamakawa, Kantarou Oota, Naoki Soeda, Yoshihide Kikuchi, Koichi Funaya, Osamu Otsuka
  • Publication number: 20020000622
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Application
    Filed: March 1, 1999
    Publication date: January 3, 2002
    Inventors: SATOSHI YAMAKAWA, YASUNORI TOKUDA, TAKUMI NAKAHATA, TAISUKE FURUKAWA, SHIGEMITSU MARUNO
  • Patent number: 6316320
    Abstract: Epitaxial silicon layers are formed on n+-source/drain regions of two MOS transistors neighboring to each other and formed on a silicon substrate, respectively. In this processing, polycrystalline silicon pieces are generated on an element isolating and insulating film and others. Thereafter, the silicon substrate is exposed to an oxygen atmosphere so that hydrogen reacts with silicon at the surfaces of the epitaxial silicon layers and the surfaces of the polycrystalline silicon pieces to form silicon oxide films and polycrystalline silicon pieces. Thereby, short-circuit between MOS transistors in neighboring memory cells is prevented, and a semiconductor device has a high electrical reliability.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: November 13, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Satoshi Yamakawa, Yuji Abe
  • Publication number: 20010019142
    Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.
    Type: Application
    Filed: September 23, 1998
    Publication date: September 6, 2001
    Inventors: TAKUMI NAKAHATA, SATOSHI YAMAKAWA, YOSHIHIKO TOYODA
  • Patent number: 6232192
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: May 15, 2001
    Assignee: Mitubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno
  • Patent number: 6228728
    Abstract: According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: May 8, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Takumi Nakahata, Shigemitsu Maruno, Kohei Sugihara, Yasutaka Nishioka, Satoshi Yamakawa, Yasunori Tokuda
  • Patent number: 4707744
    Abstract: A solid-state image sensor including pixels including photodetectors (111-148) for detecting light signals and charge sweep devices (210-240) for transferring signal charges. The pixels are arranged in first and second directions orthogonal to each other. A transfer gate scanning circuit (600) sequentially selects a pixel row from a plurality of pixel rows arranged in a second direction. A charge sweep device scanning circuit (700) supplies readout signals to the selected pixel rows so that signal charges may be read out, a plurality of times, within a horizontal scanning interval from the photodetectors (111-148).
    Type: Grant
    Filed: August 7, 1986
    Date of Patent: November 17, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masafumi Kimata, Masao Yamawaki, Satoshi Yamakawa