Patents by Inventor Satyanarayana Nishtala
Satyanarayana Nishtala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5907485Abstract: This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.Type: GrantFiled: March 31, 1995Date of Patent: May 25, 1999Assignee: Sun Microsystems, Inc.Inventors: William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin B. Normoyle, Leslie Kohn, Louis F. Coffin, III
-
Patent number: 5905998Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.Type: GrantFiled: May 19, 1997Date of Patent: May 18, 1999Assignee: Sun Microsystems, Inc.Inventors: Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F. Coffin, III
-
Patent number: 5892957Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.Type: GrantFiled: June 3, 1997Date of Patent: April 6, 1999Assignee: Sun Microsystems, Inc.Inventors: Kevin B. Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Sun-Den Chen, Charles E. Narad
-
Patent number: 5862356Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.Type: GrantFiled: June 4, 1997Date of Patent: January 19, 1999Assignee: Sun Microsystems, Inc.Inventors: Kevin B. Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III
-
Patent number: 5737755Abstract: A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.Type: GrantFiled: February 12, 1997Date of Patent: April 7, 1998Assignee: Sun Microsystems, Inc.Inventors: Zahir Ebrahim, Satyanarayana Nishtala, William Van Loo, Kevin Normoyle, Leslie Kohn, Louis F. Coffin, III
-
Patent number: 5710891Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.Type: GrantFiled: March 31, 1995Date of Patent: January 20, 1998Assignee: Sun Microsystems, Inc.Inventors: Kevin B. Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Louis F. Coffin, III
-
Patent number: 5706463Abstract: A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.Type: GrantFiled: May 12, 1997Date of Patent: January 6, 1998Assignee: Sun Microsystems, Inc.Inventors: Zahir Ebrahim, Satyanarayana Nishtala, William Van Loo, Kevin Normoyle, Leslie Kohn, Louis F. Coffin, III
-
Patent number: 5692197Abstract: A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups.Type: GrantFiled: March 31, 1995Date of Patent: November 25, 1997Assignee: Sun Microsystems, Inc.Inventors: Charles E. Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin B. Normoyle, Louis F. Coffin, III, Leslie Kohn
-
Patent number: 5689713Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.Type: GrantFiled: April 20, 1995Date of Patent: November 18, 1997Assignee: Sun Microsystems, Inc.Inventors: Kevin B. Normoyle, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Sun-Den Chen, Charles E. Narad
-
Patent number: 5684977Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect.Type: GrantFiled: March 31, 1995Date of Patent: November 4, 1997Assignee: Sun Microsystems, Inc.Inventors: William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Paul Loewenstein, Louis F. Coffin, III
-
Patent number: 5657472Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors.Type: GrantFiled: March 31, 1995Date of Patent: August 12, 1997Assignee: Sun Microsystems, Inc.Inventors: William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie Kohn, Louis F. Coffin, III, Charles E. Narad
-
Patent number: 5655100Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.Type: GrantFiled: March 31, 1995Date of Patent: August 5, 1997Assignee: Sun Microsystems, Inc.Inventors: Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F. Coffin, III
-
Patent number: 5644753Abstract: A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory.Type: GrantFiled: September 17, 1996Date of Patent: July 1, 1997Assignee: Sun Microsystems, Inc.Inventors: Zahir Ebrahim, Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo
-
Patent number: 5634068Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems include a port that transmits and receives data as data packets of a fixed size. At least two of the sub-systems are data processors, each having a respective cache memory and a respective set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. The system controller maintains a set of duplicate cache tags (Dtags) for each of the data processors. The data processors each include master cache logic for updating the master cache tags, while the system controller includes logic for updating the duplicate cache tags.Type: GrantFiled: March 31, 1995Date of Patent: May 27, 1997Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Kevin Normoyle, Leslie Kohn, Louis F. Coffin, III
-
Patent number: 5581729Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor.Type: GrantFiled: March 31, 1995Date of Patent: December 3, 1996Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Paul Loewenstein, Sue K. Lee, Louis F. Coffin III
-
Patent number: 5181167Abstract: Heatpipe elements having a thin flat, rectangular geometry are contstructed according to known heatpipe techniques. An electronic circuit module incorporating multiple discrete and integrated circuit elements is integrally imbedded into a recessed top exterior surface of each heatpipe element. The heatpipe elements are longer in one dimension that the circuit modules imbedded therein, the excess length being partitioned equally on each side of a circuit module. The remaining opposing edges of each circuit module equally overhanging the lateral edges of the heatpipe are configured as area array connectors. The resultant heatpipe/circuit module forms bilateral thermal contact areas for thermally contacting complementary surfaces of immediately adjoining heatpipe/circuit modules. Circuit modules electrically contact preceding and succeeding circuit modules via stacking connectors interposed between the respective area array connectors.Type: GrantFiled: December 2, 1991Date of Patent: January 19, 1993Assignee: Sun Microsystems, Inc.Inventors: Howard L. Davidson, Satyanarayana Nishtala