Patents by Inventor Satyanarayana SAHU
Satyanarayana SAHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11133803Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: May 7, 2020Date of Patent: September 28, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
-
Patent number: 10965289Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: February 4, 2019Date of Patent: March 30, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
-
Publication number: 20200266821Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
-
Publication number: 20190173473Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: February 4, 2019Publication date: June 6, 2019Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
-
Patent number: 10236886Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: December 28, 2016Date of Patent: March 19, 2019Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
-
Patent number: 10146900Abstract: Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.Type: GrantFiled: September 17, 2015Date of Patent: December 4, 2018Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Renukprasad Shreedhar Hiremath, Radhika Vinayak Guttal
-
Publication number: 20180183439Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
-
Patent number: 9960231Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.Type: GrantFiled: June 17, 2016Date of Patent: May 1, 2018Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Hyeokjin Bruce Lim, Satyanarayana Sahu, Venugopal Boynapalli
-
Patent number: 9958918Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.Type: GrantFiled: May 23, 2016Date of Patent: May 1, 2018Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
-
Patent number: 9886540Abstract: Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.Type: GrantFiled: September 17, 2015Date of Patent: February 6, 2018Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Renukprasad Shreedhar Hiremath, Radhika Vinayak Guttal
-
Publication number: 20170365657Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.Type: ApplicationFiled: June 17, 2016Publication date: December 21, 2017Inventors: Xiangdong CHEN, Hyeokjin Bruce LIM, Satyanarayana SAHU, Venugopal BOYNAPALLI
-
Patent number: 9831272Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.Type: GrantFiled: September 13, 2016Date of Patent: November 28, 2017Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Venugopal Boynapalli, Satyanarayana Sahu, Hyeokjin Lim, Mukul Gupta
-
Publication number: 20170336840Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Inventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
-
Publication number: 20170287933Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.Type: ApplicationFiled: September 13, 2016Publication date: October 5, 2017Inventors: Xiangdong CHEN, Venugopal BOYNAPALLI, Satyanarayana SAHU, Hyeokjin LIM, Mukul GUPTA
-
Patent number: 9640522Abstract: In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.Type: GrantFiled: April 19, 2016Date of Patent: May 2, 2017Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Vinod Gupta, Xiangdong Chen, Triveni Rachapalli
-
Patent number: 9634026Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.Type: GrantFiled: July 13, 2016Date of Patent: April 25, 2017Assignee: QUALCOMM INCORPORATEDInventors: Satyanarayana Sahu, Xiangdong Chen, Ramaprasath Vilangudipitchai, Dorav Kumar
-
Publication number: 20170083653Abstract: Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Satyanarayana Sahu, Renukprasad Shreedhar Hiremath, Radhika Vinayak Guttal
-
Patent number: 9577639Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.Type: GrantFiled: September 24, 2015Date of Patent: February 21, 2017Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Bruce Lim, Mukul Gupta, Hananel Kang, Chih-lung Kao, Radhika Guttal
-
Patent number: 9564881Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.Type: GrantFiled: May 22, 2015Date of Patent: February 7, 2017Assignee: QUALCOMM INCORPORATEDInventors: Qi Ye, Steven James Dillen, Animesh Datta, Zhengyu Duan, Satyanarayana Sahu, Praveen Narendranath
-
Publication number: 20160344374Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: Qi YE, Steven James DILLEN, Animesh DATTA, Zhengyu DUAN, Satyanarayana SAHU, Praveen NARENDRANATH