Patents by Inventor Satyavathi Akella

Satyavathi Akella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive variable length pulse synchronizer
    Patent number: 7680231
    Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: March 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John E. Angello, Satyavathi Akella, Kiyoshi Kase, May Len
  • Adaptive variable length pulse synchronizer
    Publication number: 20070183549
    Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 9, 2007
    Applicant: Freescale Semiconductor, Inc
    Inventors: John Angello, Satyavathi Akella, Kiyoshi Kase, May Len