Patents by Inventor Satyendra Singh Chauhan
Satyendra Singh Chauhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930590Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: GrantFiled: March 31, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Patent number: 11908780Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.Type: GrantFiled: November 3, 2021Date of Patent: February 20, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
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Patent number: 11658130Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.Type: GrantFiled: December 31, 2020Date of Patent: May 23, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tianyi Luo, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Osvaldo Jorge Lopez, Lance Cole Wright
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Patent number: 11557722Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: January 6, 2021Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Patent number: 11495580Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: GrantFiled: November 8, 2018Date of Patent: November 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Publication number: 20220208692Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Applicant: Texas Instruments IncorporatedInventors: Tianyi Luo, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Osvaldo Jorge Lopez, Lance Cole Wright
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Publication number: 20220210911Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: ApplicationFiled: March 31, 2021Publication date: June 30, 2022Inventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Publication number: 20220115308Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.Type: ApplicationFiled: November 3, 2021Publication date: April 14, 2022Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
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Patent number: 11177197Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.Type: GrantFiled: September 25, 2019Date of Patent: November 16, 2021Assignee: Texas Instruments IncorporatedInventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
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Publication number: 20210159403Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: ApplicationFiled: January 6, 2021Publication date: May 27, 2021Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20210090980Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.Type: ApplicationFiled: September 25, 2019Publication date: March 25, 2021Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
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Patent number: 10892405Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: May 7, 2019Date of Patent: January 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20200357987Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20190088628Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Inventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Patent number: 10128219Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: GrantFiled: April 25, 2013Date of Patent: November 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Publication number: 20130285260Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: ApplicationFiled: April 25, 2013Publication date: October 31, 2013Applicant: Texas Instruments IncorporatedInventors: MARIE DENISON, RICHARD SAYE, TAKAHIKO KUDOH, SATYENDRA SINGH CHAUHAN
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Patent number: 8193093Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: GrantFiled: May 18, 2011Date of Patent: June 5, 2012Assignee: Texas Instruments IncorporatedInventor: Satyendra Singh Chauhan
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Patent number: 8039309Abstract: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.Type: GrantFiled: May 7, 2008Date of Patent: October 18, 2011Assignee: Texas Instruments IncorporatedInventors: Masood Murtuza, Satyendra Singh Chauhan, Donald C. Abbott
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Publication number: 20110250720Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: ApplicationFiled: May 18, 2011Publication date: October 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Satyendra Singh CHAUHAN
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Patent number: 8017439Abstract: A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.Type: GrantFiled: January 26, 2010Date of Patent: September 13, 2011Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Singh Chauhan