Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one array plane while the write path writes in another array plane and one or more blocks are being erased. The uniform block size permits a symmetric layout and provides maximum flexibility in storage of data, code, and parameters. The uniform block size also allows spare blocks in the array planes to replace of any defective blocks. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution to replace addresses corresponding to defective memory elements. To reduce access delays, part of the input address such as the row address goes directly to decoders, while another part of the input address such as the block address goes to the CAM array.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A contactless Flash memory has memory cells between each pair of adjacent diffused lines and about half as many metal lines as diffused lines. Bank select cells at the top of a bank in the memory connect the metal lines to pairs of diffused lines that are offset relative to pairs of diffused lines connected to the metal lines via bank select cells at the bottom of the bank. Decoding circuits activate the bank select cells at one end of a bank to access memory cells in odd-numbered columns of the bank and activate the bank select cells at the other end to access memory cells in even-numbered columns of the bank. For the access, all metal lines to one side of a selected memory cell are grounded, while all metal lines on the other side are biased for reading or programming of the selected memory cell.

Abstract: A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Abstract: A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Abstract: Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.

Abstract: A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. The Flash memory includes separate internal read and write paths connected to multiple array planes to permit a read in one array plane during a write in another array plane, further a third array plane can erase a block during the read and write operations. The uniform size, which permits a symmetric layout, is selected for efficient storage of parameters to provide maximum flexibility in allocation of storage. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A compact contactless Flash memory architecture has memory cells instead of isolation regions between adjacent diffused lines in rows of a bank and thereby increases the density of memory cells in the bank when compared to prior architectures. Diffused lines in the bank can be used as virtual ground lines or as bit lines depending on which column of the bank is selected for access. The architecture includes about half as many metal lines as diffused lines, and most bank select cells operate to connect respective metal lines to a respective pairs of diffused lines. Pairs of diffused lines connected to the bank select cells at one end of the bank are offset relative to pairs of diffused lines connected to the bank select cells at the other end of the bank.

Abstract: A contactless Flash memory uses a bank architecture with bank select devices and/or source line contacts at both ends of each bank. During programming, bank select devices at both ends of the bank supply currents to the memory cell being programmed, and/or diffused source lines conduct currents in both directions away from the memory cell being programmed. The multiple current paths reduce the current in any portion of the diffused lines and thereby reduce voltage drops in the diffused lines during programming. Accordingly, banks can have longer diffused lines (e.g., with twice as many cells per column of a bank) and still employ small bank select devices. The longer bank columns and smaller bank select devices result in an overall decrease in integrated circuit area for bank select devices, even though each bank has two bank select devices per diffused bit line.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A multi-bit-per-cell non-volatile memory stores different portions of a data stream using different numbers of bits per cell. In particular, data that requires a high degree of data integrity (e.g., the header of a data frame) is stored using a relatively small number of bits per memory cell. Data that is more error-tolerant (e.g., the main data representing music, images, or video) is stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. Read circuitry decodes an output data stream and determines a number of bits read from each memory cell to generate the data stream. One such memory includes a decoder in the write circuitry and a decoder in the read circuitry, and another embodiment includes a single decoder that the write and read circuits share.

Abstract: A multi-bit-per-cell non-volatile memory periodically reads and rewrites data and thereby refreshes threshold voltages and removes the effects of threshold voltage drift. Accordingly, threshold voltages are kept in narrower ranges, and the narrow ranges allow more distinct levels for data values and allows storage of more bits per cell. A refresh interval is according to the size of windows for different multi-bit values and the measured or expected rate of threshold voltage drift. An on-chip refresh timer and arbitration logic selects when to initiate a refresh operation. A refresh can use a data buffer for temporary storage or can directly write data from one memory location to another. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits.

Abstract: A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of Flash memory cells in a column, and each match line is a source line coupled to sources of Flash memory cells in a row. A 2-T CAM cell includes a pair of non-volatile devices coupled to the same word line and match line. Each non-volatile device can be a floating-gate transistor, a Flash memory cell, or a shared-floating-gate (SFG) device. An erase of a CAM word applies erase voltages to the word and match lines associated with the word. The erase does not depend on the bit line voltages. Accordingly, the CAM array can simultaneously perform a search and an erase. With SFG devices, the CAM array can also simultaneously perform a search and a program operation.

Abstract: A read operation for a multi-level or a multi-bit-per-cell non-volatile memory biases a selected row line cell at a fixed voltage that is above the maximum possible threshold voltage representing data and changes the column line load for a selected column line. The column line load that corresponds to the trip-point of a sense amplifier indicates the data stored in the memory cell coupled to the selected row and column lines. A corresponding write process uses the same fixed row line voltage for both program and verify cycles. The programming voltage can be the same as the row line voltage for the read operation or can depend on the data value being written. To better control programming, the duration of the program cycles and/or the load on the drain or source of the selected memory cell during a program cycle varies with time and depends on the value being written. One memory in accordance with the invention includes variable column line loads for use during read and write operations.

Abstract: Input partitioning logic is coupled to bit-lines of a content addressable memory (CAM) array having four-transistor (4-T) non-volatile Flash CAM cells. Prior to a program or search operation on the 4-T Flash CAM cells, two input data bits and their complements are applied to the input partitioning logic, which can be two-input NAND, NOR, AND, or OR gates. By selecting the appropriate values for the input bits, individual ones of the memory cells in the 4-T CAM cell can be programmed, or a desired two-bit pattern can be searched. The use of input partitioning logic prior to applying the search and program voltages to the bit-lines of the CAM cell results in substantially less voltage transitions during searches and less required programming current because fewer Flash memory cells are required to be programmed. Consequently, power consumption while operating the CAM array is substantially reduced, and the Flash memory cell endurance is effectively increased.

Abstract: An SRAM-based CAM cell and CAM array architecture reduce transistor count and memory size by replacing pass transistors and search transistors of conventional SRAM-base CAM cells with a pair of transistors having gates coupled to bit lines. The two bit-line-controlled transistors in a CAM cell are between storage nodes and a word/match line for the CAM cell. The sizes of pull-up and pull-down devices in the CAM cells are selected so that grounding a storage node to a word/match line through one of the two bit-line-controlled transistors can change the bit stored in a CAM cell, but applying a voltage (near the supply voltage) from the word/match line through either of the two bit-line-controlled transistors to a storage node cannot change the bit or data stored in a CAM cell. Accordingly, a write operation grounds a selected word/match line and applies a voltage to the unselected word/match lines. A search operation charges all word/match lines and senses the word/match lines.

Abstract: A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage.