Abstract: Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Abstract: A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

Abstract: Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

Abstract: Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

Abstract: A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

Abstract: Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Abstract: An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxillary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

Abstract: An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: There is disclosed herein integrated circuitry, comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analog converter circuitry.

Abstract: There is disclosed herein integrated circuitry,comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.

Abstract: A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.

Abstract: A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.

Abstract: Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another.

Abstract: A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.

Abstract: A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.

Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analog-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analog converter, wherein: the first switching-circuitry unit is configured to sample an input analog signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analog signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of dock signals have the same specifications as one another.

Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.

Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.