Patents by Inventor Saul Ferguson

Saul Ferguson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100311564
    Abstract: Dielectric oxide materials prepared by producing a sol from a mixture of a metal oxide precursor, a solvent, and an epoxide, and preparing a metal oxide material from the sol. In various versions, the mixture can also include a cosolvent, one or more additional metal oxide precursors, water, or a precursor to a glassforming oxide, or any combination thereof. The prepared dielectric oxide materials can be in the form of thin films having high ? values, low electrical leakage, and low dielectric loss tangent values.
    Type: Application
    Filed: March 23, 2010
    Publication date: December 9, 2010
    Inventors: Mark Phillps, Travis Thoms, Saul Ferguson
  • Patent number: 7741189
    Abstract: A method of embedding thick-film fired-on-foil capacitors includes entirely covering the dielectric with an encapsulating electrode to avoid cracking in the dielectric due to shrinkage and temperature coefficient of expansion differences between the electrode and dielectric.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: June 22, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Richard Ray Traylor
  • Patent number: 7701052
    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 20, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson
  • Patent number: 7649361
    Abstract: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 19, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William Borland, Saul Ferguson, Diptarka Majumdar, Daniel I. Amey
  • Patent number: 7586198
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 8, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Matthew C. Snogren, Richard H. Snogren
  • Publication number: 20080145995
    Abstract: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 19, 2008
    Applicant: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Daniel I. Amey
  • Publication number: 20070090511
    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 26, 2007
    Inventors: William Borland, Saul Ferguson
  • Patent number: 7178229
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 20, 2007
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Matthew C. Snogren, Richard H. Snogren
  • Publication number: 20060282999
    Abstract: Disclosed is an improved method of embedding capacitors in printed wiring boards (PWB) made from thick film dielectrics and electrodes.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 21, 2006
    Inventors: Diptarka Majumdar, Saul Ferguson
  • Publication number: 20060284280
    Abstract: A method of embedding thick-film fired-on-foil capacitors includes entirely covering the dielectric with an encapsulating electrode to avoid cracking in the dielectric due to shrinkage and temperature coefficient of expansion differences between the electrode and dielectric.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 21, 2006
    Inventors: William Borland, Saul Ferguson, Diptarka Majumdar, Richard Traylor
  • Publication number: 20060254812
    Abstract: A method of forming printed wiring boards having embedded thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from contacting with and damaging the capacitor layers and forming vias directly between the capacitor electrodes and the board circuitry.
    Type: Application
    Filed: July 14, 2006
    Publication date: November 16, 2006
    Inventors: William Borland, Saul Ferguson, Hena Pyada
  • Patent number: 7100277
    Abstract: A method of forming printed wiring boards having embedded thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from contacting with and damaging the capacitor layers and forming vias directly between the capacitor electrodes and the board circuitry.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: September 5, 2006
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Hena Pyada
  • Publication number: 20060101639
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Application
    Filed: December 29, 2005
    Publication date: May 18, 2006
    Inventors: William Borland, Saul Ferguson, Diptarka Majumdar, Matthew Snogren, Richard Snogren
  • Publication number: 20060002097
    Abstract: A method of embedding thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from coming in contact with and damaging the capacitor layers.
    Type: Application
    Filed: July 1, 2004
    Publication date: January 5, 2006
    Inventors: William Borland, Saul Ferguson, Hena Pyada
  • Publication number: 20050111206
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Application
    Filed: November 20, 2003
    Publication date: May 26, 2005
    Inventors: William Borland, Saul Ferguson, Diptarka Majumdar, Matthew Snogren, Richard Snogren
  • Publication number: 20040231885
    Abstract: In a printed wiring board, a plurality of stacked innerlayer panels have capacitors connected in parallel by connecting a first electrode of a first panel with a first electrode of a second panel, and similarly connecting second electrodes of the first and second panels. The innerlayer panel having capacitors connected in parallel provides a high capacitance in a small x-y area. An alternate printed wiring board has a capacitor having a first foil electrode, and second and third electrodes located on opposite sides of the first foil electrode. Yet another printed wiring board has capacitors formed as an array of discrete foil electrodes spaced from an array of discrete printed electrodes. Forming discrete interconnected electrodes allows the electrodes to be fired without excessive thermal coefficient of expansion stresses damaging the electrodes.
    Type: Application
    Filed: February 4, 2004
    Publication date: November 25, 2004
    Inventors: William J. Borland, Saul Ferguson, David R. McGregor
  • Publication number: 20040108134
    Abstract: A printed wiring board (PWB) has stacked innerlayer panels comprised of passive circuit elements. The passive elements can include capacitors with electrode terminations located within the footprints of the capacitor electrodes. The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors.
    Type: Application
    Filed: September 16, 2003
    Publication date: June 10, 2004
    Inventors: William J. Borland, Saul Ferguson, David R. McGregor