Patents by Inventor Saurabh Chaubey

Saurabh Chaubey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low dropout regulator with smart offset
    Patent number: 10873257
    Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Regents of the University of Minnesota
    Inventors: Ramesh Harjani, Saurabh Chaubey
  • LOW DROPOUT REGULATOR WITH SMART OFFSET
    Publication number: 20200144913
    Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.
    Type: Application
    Filed: September 6, 2019
    Publication date: May 7, 2020
    Inventors: Ramesh Harjani, Saurabh Chaubey
  • Ultra high density integrated composite capacitor
    Patent number: 9812457
    Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 7, 2017
    Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Ramesh Harjani, Rakesh Kumar Palani, Saurabh Chaubey
  • ULTRA HIGH DENSITY INTEGRATED COMPOSITE CAPACITOR
    Publication number: 20170301675
    Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Inventors: Ramesh Harjani, Rakesh Kumar Palani, Saurabh Chaubey