Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

Abstract: Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive levels and electrically insulative levels. A first opening is formed through the first hardmask and the stack. Cavities are formed to extend into the electrically conductive levels. A fill material is formed within the first opening and within the cavities. A second hardmask is formed over the first hardmask and over the fill material. A second opening is formed through the second hardmask. The second opening is narrower than the first opening. The second opening is extended into the fill material to form an upwardly-opening container from the fill material. Sidewalls of the upwardly-opening container are removed, while leaving the fill material within the cavities as a plurality of vertically-stacked structures.

Abstract: Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive levels and electrically insulative levels. A first opening is formed through the first hardmask and the stack. Cavities are formed to extend into the electrically conductive levels. A fill material is formed within the first opening and within the cavities. A second hardmask is formed over the first hardmask and over the fill material. A second opening is formed through the second hardmask. The second opening is narrower than the first opening. The second opening is extended into the fill material to form an upwardly-opening container from the fill material. Sidewalls of the upwardly-opening container are removed, while leaving the fill material within the cavities as a plurality of vertically-stacked structures.

Abstract: Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

Abstract: Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.