Patents by Inventor Saurabh Pijuskumar Sinha
Saurabh Pijuskumar Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210390059Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Alejandro Rico Carro, Douglas Joseph, Saurabh Pijuskumar Sinha
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Publication number: 20210389520Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.Type: ApplicationFiled: October 23, 2019Publication date: December 16, 2021Inventors: Vinay Vashishtha, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Gregory Munson Yeric
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Patent number: 11126778Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: GrantFiled: May 18, 2020Date of Patent: September 21, 2021Assignee: Arm LimitedInventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Patent number: 11120191Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.Type: GrantFiled: March 16, 2020Date of Patent: September 14, 2021Assignee: Arm LimitedInventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Patent number: 11081469Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.Type: GrantFiled: September 24, 2019Date of Patent: August 3, 2021Assignee: ARM LIMITEDInventors: Saurabh Pijuskumar Sinha, Joel Thornton Irby, Supreet Jeloka
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Patent number: 11011227Abstract: Methods, systems and devices for operation of non-volatile memory device are described herein. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the non-volatile memory element.Type: GrantFiled: June 15, 2018Date of Patent: May 18, 2021Assignee: ARM Ltd.Inventors: Supreet Jeloka, Shidhartha Das, Mudit Bhargava, Saurabh Pijuskumar Sinha, James Edwards Myers
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Publication number: 20210091041Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: Saurabh Pijuskumar SINHA, Joel Thornton IRBY, Supreet JELOKA
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Publication number: 20210081508Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Xiaoqing Xu, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Stephen Lewis Moore, Mudit Bhargava
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Patent number: 10922608Abstract: Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.Type: GrantFiled: March 8, 2017Date of Patent: February 16, 2021Assignee: ARM LTDInventors: Naveen Suda, Vikas Chandra, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Shidhartha Das
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Publication number: 20210028788Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Inventors: Xiaoqing Xu, Saurabh Pijuskumar Sinha, Sheng-En Hung, Chien-Ju Chao
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Patent number: 10825745Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.Type: GrantFiled: October 29, 2019Date of Patent: November 3, 2020Assignee: ARM LIMITEDInventors: Saurabh Pijuskumar Sinha, Xiaoqing Xu, Joel Thornton Irby, Mudit Bhargava
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Publication number: 20200279067Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Publication number: 20200257841Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Saurabh Pijuskumar SINHA, Kyungwook CHANG, Brian Tracy CLINE, Ebbin Raney SOUTHERLAND, JR.
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Publication number: 20200218845Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Inventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Patent number: 10678985Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.Type: GrantFiled: August 31, 2016Date of Patent: June 9, 2020Assignee: ARM LimitedInventors: Saurabh Pijuskumar Sinha, Kyungwook Chang, Brian Tracy Cline, Ebbin Raney Southerland, Jr.
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Patent number: 10657218Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: GrantFiled: November 29, 2017Date of Patent: May 19, 2020Assignee: Arm LimitedInventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Patent number: 10641953Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.Type: GrantFiled: October 26, 2018Date of Patent: May 5, 2020Assignee: Arm LimitedInventors: Vinay Vashishtha, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Gregory Munson Yeric
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Publication number: 20200132929Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Vinay Vashishtha, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Gregory Munson Yeric
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Patent number: 10599806Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs.Type: GrantFiled: March 28, 2018Date of Patent: March 24, 2020Assignee: Arm LimitedInventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Publication number: 20190385675Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the correlated electron element.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Supreet Jeloka, Shidhartha Das, Mudit Bhargava, Saurabh Pijuskumar Sinha, James Edwards Myers