Abstract: An encoding system analyzes a data file to determine if portions of the data file include significant disparities in symbol probability. Huffman coding trees are produced for each of the portions of the data file and the portions are separately encoded according to specific Huffman coding trees. Encoded portions and the corresponding Huffman coding tree are packaged together and transmitted to a decoder. The encoder and decoder processes portions using different Huffman coding trees in parallel via multiple processors or processing cores.

Abstract: The node communication controller (NCC) suitable for use in a line-replaceable unit (LRU) of a modular avionics system may include one or more embedded processors configured to host one or more functions associated with at least one avionics module of an avionics system, an input/output (I/O) controller, and one or more I/O ports, wherein the I/O controller is configured to route data between the one or more embedded processors and the at least one avionics module via the one or more I/O ports and a network communication bus, wherein the I/O controller is further configured to route data between a host processor of the LRU and an additional avionics module via the one or more I/O ports and the network communication bus.

Abstract: Systems and techniques for implementing fault-tolerant communication channels and features in communication systems. Selected commercial-off-the-shelf devices can be integrated in such systems to reduce the cost.

Abstract: In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, cyclic redundancy check (CRC), and byte count check operations. The I2C bus controller may include a control unit connected to an I2C core module having a base address. The I2C bus controller may also include a second I2C core module having a base address plus one (BP1). The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or, in the master mode, from itself through the BP1 I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus.

Abstract: A fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. Each of the memory cells comprises a pair memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In accordance with one feature of the invention, the memory systematically searches for an error in response to an error signal and corrects the error found by the search.