Abstract: A level shifter includes a first branch and a second branch. A trigger of the first branch is coupled to a low voltage input, an inverted high voltage output and a ground. A latch of the first branch is coupled to the inverted high voltage output and a high voltage output. A power gate of the first branch is coupled to an inverted low voltage input, the latch of the first branch and a high voltage supply. A trigger of the second branch is coupled to the inverted low voltage input, the high voltage output and the ground. A latch of the second branch is coupled to the high voltage output and the inverted high voltage output. A power gate of the second branch is coupled to the low voltage input, the latch of the second branch and the high voltage supply.

Abstract: A level shifter includes a first branch and a second branch. A trigger of the first branch is coupled to a low voltage input, an inverted high voltage output and a ground. A latch of the first branch is coupled to the inverted high voltage output and a high voltage output. A power gate of the first branch is coupled to an inverted low voltage input, the latch of the first branch and a high voltage supply. A trigger of the second branch is coupled to the inverted low voltage input, the high voltage output and the ground. A latch of the second branch is coupled to the high voltage output and the inverted high voltage output. A power gate of the second branch is coupled to the low voltage input, the latch of the second branch and the high voltage supply.

Abstract: A Static Random Access Memory (SRAM) cell having high stability and low leakage is provided. The SRAM cell includes a pair of cross-coupled inverters providing differential storage of a data bit. Power to the SRAM cell is provided by a read word line (RWL) signal, which is also referred to herein as a read control signal. During read operations, the RWL signal is pulled to a voltage level that forces the SRAM cell to a full-voltage state. During standby, the RWL signal is pulled to a voltage level that forces the SRAM cell to a voltage collapsed state in order to reduce leakage current, or leakage power, of the SRAM cell. A read-transistor providing access to the bit stored by the SRAM cell is coupled to the SRAM cell via a gate of the read transistor, thereby decoupling the stability of the SRAM cell from the read operation.