Abstract: The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.

Abstract: The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.

Abstract: The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.

Abstract: An error correction and miscorrection detection apparatus includes a memory buffer for storing user data contained in a data signal. A syndrome computer circuit generates a plurality of EDC syndromes form an EDC codeword. The EDC codeword includes user data encoded with a plurality of m-bit EDC parity symbols. The EDC codeword is encoded with plurality of n-bit ECC parity symbols to form the data signal, such that m>n. An ECC error correction circuit corrects the user data with an error signal generated for each corruption of the data signal. A completion is signal generated once correction of the EDC codeword is complete. A syndrome fix-up circuit is configured to adjust the EDC syndromes based on the received error signals. Once the completion signal is received, a miscorrection by the ECC error correction circuit is detected if a value of the adjusted syndromes is not equal to zero.

Abstract: The present invention pertains to a method for determining if data read from a storage medium has been read from physical block address (PBA) other than the expected PBA. Data that is stored on the data storage medium is encoded in accordance with a protocol that includes randomizing the data and combining the first k.times.2t bytes of the data with a PBA string, where t is the error correction capacity associated with the error correction technique used in the data storage system and k is the number of bytes of the PBA that are used in the PBA string. In addition, the data is k-way interleaved with parity data appended to it. When the data is read from the data storage medium, the data is decoded using a scheme corresponding to the encoding protocol. If errors are present in the data and exceed the error correction capacity, the first 2t bytes of each interleave are marked as erasures and a second correction is performed by an error correction unit.