Patents by Inventor Scot M. Graham
Scot M. Graham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7746720Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.Type: GrantFiled: July 17, 2007Date of Patent: June 29, 2010Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Venkatraghavan Bringivijayaraghavan, Abhay S. Dixit, Scot M. Graham, Stephen R. Porter, Ethan A. Williford
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Patent number: 7336522Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.Type: GrantFiled: July 19, 2006Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Stephen R. Porter, Scot M. Graham, Ethan A. Williford, Kevin G. Duesman
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Patent number: 7257043Abstract: A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.Type: GrantFiled: February 21, 2006Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Stephen R. Porter, Scot M. Graham, Steven E. Howell
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Patent number: 7245548Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.Type: GrantFiled: July 27, 2004Date of Patent: July 17, 2007Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Venkatraghavan Bringivijayaraghavan, Abhay S. Dixit, Scot M. Graham, Stephen R. Porter, Ethan A. Williford
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Patent number: 7142446Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.Type: GrantFiled: July 29, 2004Date of Patent: November 28, 2006Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Stephen R. Porter, Scot M. Graham, Ethan A. Williford, Kevin G. Duesman
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Patent number: 7020039Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.Type: GrantFiled: November 29, 2004Date of Patent: March 28, 2006Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Stephen R. Porter, Scot M. Graham, Steven E. Howell
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Patent number: 6834019Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.Type: GrantFiled: August 29, 2002Date of Patent: December 21, 2004Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Stephen R. Porter, Scot M. Graham, Steven E. Howell
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Patent number: 6816425Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: February 11, 2004Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20040158690Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: February 11, 2004Publication date: August 12, 2004Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Patent number: 6717873Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: December 12, 2002Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20040042309Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Luan C. Tran, Stephen R. Porter, Scot M. Graham, Steven E. Howell
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Publication number: 20030081476Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: December 12, 2002Publication date: May 1, 2003Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Patent number: 6556467Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.Type: GrantFiled: August 29, 2001Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Scot M. Graham
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Patent number: 6515925Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: GrantFiled: March 15, 2001Date of Patent: February 4, 2003Assignee: Micron Technology, Inc.Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Publication number: 20020131311Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Inventors: Scot M. Graham, Scott J. Derner, Stephen R. Porter
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Patent number: 6301172Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.Type: GrantFiled: February 27, 2001Date of Patent: October 9, 2001Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Scot M. Graham
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Patent number: 4343441Abstract: An apparatus for driving a replaceable reel of magnetic tape is disclosed. The apparatus comprises a magnetic clamp for holding the reel to a cup-shaped driving member. The cup-shaped driving member carries a doughnut-shaped magnet and is provided with an integral center shunt member which extends into the center of the reel when the reel is positioned in driving engagement. The reel is provided with a central opening, and a circular metal plate is attached to the bottom surface of the reel hub to be attracted by the doughnut-shaped magnet. By extending the center pole piece a predetermined distance above the plane of the doughtnut-shaped magnet, the extended center pole piece provides an easy path for the flux as the members are being separated, since a relatively small air gap is maintained between the extended center pole and the central opening of the disk.Type: GrantFiled: December 24, 1980Date of Patent: August 10, 1982Assignee: International Business Machines CorporationInventor: Scot M. Graham