Abstract: Embodiments include a method for configuring basic input/output system (BIOS) of a wagering game machine. The method can include: initializing a processor and chipset residing on an embedded computer module residing in the wagering game machine, wherein the BIOS resides on a carrier board connected to the embedded computer module; identifying, under control of code in the BIOS, the embedded computer module as a particular one of a plurality of embedded computer modules, wherein the BIOS includes code for configuring each of the plurality of embedded computer modules; initializing, using code of the BIOS configured for the particular one of the plurality of embedded computer modules, input/output devices connected to the carrier board and embedded computer module; launching, under control of the BIOS, an operating system in the wagering game machine; presenting a wagering game on the wagering game machine, wherein the presenting utilizes information received from the input/output devices.

Abstract: In some embodiments, a wagering game machine includes: a carrier board comprising a first network port and a second network port, the first network port having a first network address and the second network port having a second network address; a processor located on the carrier board; a first nonvolatile memory located on the carrier board and communicatively coupled to the first network port, the first nonvolatile memory configured to store the first network address; and a second nonvolatile memory located on the carrier board, wherein the second nonvolatile memory is configured to store Basic Input and Output System (BIOS) code that includes a system BIOS code and an application BIOS code, wherein the BIOS code is hardware write-protected, wherein the processor is configured to derive the second network address from the first network address during execution of boot-up operations of the apparatus.

Abstract: A system for shutting down and resetting an embedded system having a general purpose computing platform. A push button is provided for generating a push button reset signal to the shutdown and reset manager. The shutdown and reset manager receives the management reset signal and initiates a shutdown of the operating system. When the operating system has shutdown, the user presses the push button again. The second receipt of the push button reset signal initiates a hardware reset.

Abstract: An apparatus and method for activating a switch with a circuit board ejector includes a circuit board and a switch assembly including the switch for transitioning the circuit board from a first mode to a second mode and vice versa. The switch assembly is attached to the circuit board, and the circuit board ejector is rotatably attached to the circuit board to allow the circuit board ejector to be positioned in an unlatched position and a latched position. The circuit board ejector includes a hook portion and a bracket arm wherein the bracket arm of the circuit board ejector activates the switch assembly and causes the circuit board to transition from the first mode to the second mode and vice versa.

Abstract: A system for shutting down and resetting an embedded system having a general purpose computing platform. A shutdown management driver generates a management reset according to a predetermined set of shutdown conditions. The shutdown and reset manager receive the management reset signal and initiate a shutdown of the operating system. When the operating system has shutdown, the second receipt of the management reset signal initiates a hardware reset.

Abstract: A module incorporating flash memory chips. An interface enables power down of the chips in response to a power down signal and provides an interrupt signal indicating when all of the ready lines from the memory chips are in a ready state, thereby reducing the need for polling the status registers in the chips.

Abstract: Apparatus and method for managing transmission of digital data between a digital telephone line and a computer network. First and second modems, a telephone control circuit and a network control circuit respond to management instruction signals to execute predetermined management objectives and generate management response signals representing one or more conditions of the first and second modems, telephone control circuit and network control circuit. In response to a single packet of management signals from the network, a management circuit generates the management instruction signals and independently addresses them to one or more of the first and second modems, telephone control circuit and network control circuit.

Abstract: An improved backplane apparatus for transmitting signals to and from a modem system. The modem system includes more than one modem for transmitting data via at least one telephone line and via at least one network. The modem system has a first bus for management signal communication with the modems at a predetermined first data rate, and a second bus for transmitting data between the telephone line and the modems at a predetermined second data rate greater than the first data rate. The modem system also has a third bus for transmitting data between the modems and the network at a predetermined third data rate greater than the second data rate, and a fourth bus for distributing DC power and ground potential. The modem system defines a first impedance for terminating the first bus, a second impedance for terminating the second bus, and a third impedance for terminating the third bus.