Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.

Abstract: A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure.

Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer and the dielectric layer. The nitride layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Abstract: A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.

Abstract: The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.

Abstract: A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

Abstract: Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

Abstract: A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon nitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon nitride layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

Abstract: A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.

Abstract: A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.

Abstract: A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Abstract: The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen implantation at high dosages to prevent subsequent impurity penetration through the gate dielectric layer, e.g., B penetration, amorphizes the upper portion of the gate electrode layer resulting in concave side surfaces upon etching to form the gate electrode. Heat treatment performed after nitrogen implantation can restore sufficient crystallinity so that, after etching the gate electrode layer, the side surfaces of the resulting gate electrode are substantially parallel.

Abstract: Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.

Abstract: A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Abstract: A blood reservoir is formed with a hard outer shell housing defining at least one blood compartment. A flexible bag is mounted in the outer shell and is connected to the reservoir inlet port to allow blood to directly enter the flexible bag. The bag includes two oppositely positioned ends, one of which includes a mircoporous screen and is situated to lie partially below a minimum level attained by blood in the reservoir. The second bag end is substantially open, and includes a porous element partially coated with an antifoaming agent. The coated portion of the element is positioned above a maximum level attained by the blood in the hard shell. The potential of excessive mixing between the blood and air is reduced by controlling the expansion of the bag during blood flow.