Abstract: A voltage regulator may include a resistor-based voltage divider circuit generating a desired output voltage from a supply voltage, an output NMOS device whose source terminal may be configured as the output of the voltage regulator and whose drain terminal may be configured to receive the supply voltage, and a control circuit configured to control the output NMOS device to maintain the desired output voltage at the output of the voltage regulator. The control circuit may be configured to receive the desired output voltage from the voltage divider circuit as a first input, and to receive the output of the voltage regulator fed back as a second input to form a feedback loop.

Abstract: Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: In one embodiment, a bandgap voltage reference generating circuit is configured to generate a reference voltage, and may comprise a first PN-junction whose base-emitter voltage (VBE) exhibits a curvature with respect to temperature, where a current conducted by the first PN-junction is proportional to absolute temperature (PTAT). The voltage reference generating circuit may also include a second PN-junction coupled to the first PN-junction. A control circuit coupled to the second PN-junction may be configured to inject a control current into the second PN-junction, where the control current has a negative to absolute temperature (NTAT) characteristic, the control circuit thereby operating to effectively eliminate a curvature with respect to temperature exhibited by the bandgap voltage.

Abstract: In one set of embodiments, a circuit may be implemented to deliver accurately ratioed currents to a remotely located semiconductor device that has a substantially non-linear input-output characteristic that varies with temperature and is subject to effects of electromagnetic interference (EMI). The circuit may be configured to use common mode rejection by establishing an identical impedance at each of the two terminals of the remotely located semiconductor device, in lieu of coupling shunting capacitor(s) across the terminals, in order to reject EMI signals while performing temperature measurements using the remotely located semiconductor device. This may facilitate maintaining fast sampling times when performing temperature measurements, while providing a more effective method for handling EMI induced currents that may lead to temperature measurement errors, thereby eliminating those errors.

Abstract: In one set of embodiments, a temperature measurement system may include an analog to digital converter (ADC) to produce digital temperature readings according to a difference base-emitter voltage (?VBE) developed across a PN-junction. A clock generating circuit may be configured to provide a sampling clock used by the ADC, which in some embodiments may be a delta-sigma ADC, in performing the conversions. The clock generating circuit may be configured to change the frequency of the sampling clock a specified number of times within each one of the one or more conversion cycles to reduce an error component in the temperature measurement, where the error component is produced by an interfering signal, such as an electromagnetic interference (EMI) signal being coherent with the sampling clock, and/or a noise residing on the voltage supply and also being coherent with the sampling clock.

Abstract: A reliable, integrated POR (power-on-reset) circuit with a compact and small area. In one set of embodiments, the POR circuit comprises NMOS and PMOS devices, where a combination of the respective threshold voltages of the NMOS and PMOS devices is used to set the POR threshold. The NMOS and PMOS devices may be coupled in a configuration resulting in a POR threshold that is a function of the PMOS threshold voltage and a scaled version of the NMOS threshold voltage. The scaling factor may be a function of the transconductance parameters of the NMOS and PMOS devices. Additional NMOS devices may be configured in the POR circuit to provide hysteresis functionality, with one of the NMOS devices coupling to one of the original NMOS devices. The scaling factor used in determining the POR threshold in case of a falling supply voltage may then be a function of the transconductance parameters of the original NMOS and PMOS devices and the additional NMOS device coupling to one of the original NMOS devices.

Abstract: In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference.

Abstract: A temperature measurement device may be implemented by coupling a PN-junction, which may be comprised in a diode, to an analog-to-digital converter (ADC) that comprises an integrator. Different currents may be successively applied to the diode, resulting in different VBE values across the diode. The ?VBE values thus obtained may be successively integrated. Appropriate values for the different currents may be determined based on a set of mathematical equations, each equation relating the VBE value to the temperature of the diode, the current applied to the diode and parasitic series resistance associated with the diode. When the current sources with the appropriate values are sequentially applied to the diode and the resulting diode voltage differences are integrated by the integrator comprised in the ADC, the error in the temperature measurement caused by series resistance is canceled in the ADC, and an accurate temperature reading of the diode is obtained from the output of the ADC.

Abstract: A temperature sensor circuit and system providing accurate readings using a temperature diode whose ideality factor may fall within a determined range. In one set of embodiments a change in diode junction voltage (?VBE) proportional to the temperature of the diode is captured and provided to an ADC, which may perform required signal conditioning functions on ?VBE, and provide a numeric value output corresponding to the temperature of the diode. Errors in the measured temperature that might result from using diodes with ideality factors that differ from an expected ideality factor may be eliminated by programming the system to account for differing ideality factors. The gain of the temperature sensor may be matched to the ideality factor of the temperature diode by using an accurate, highly temperature stable reference voltage of the ADC to set the gain of the temperature measurement system.

Abstract: A temperature measurement device may be implemented by coupling a PN-junction, which may be comprised in a diode, to an analog-to-digital converter (ADC) that comprises an integrator. Different currents may be successively applied to the diode, resulting in different VBE values across the diode. The ?VBE values thus obtained may be successively integrated. Appropriate values for the different currents may be determined based on a set of mathematical equations, each equation relating the VBE value to the temperature of the diode, the current applied to the diode and parasitic series resistance associated with the diode. When the current sources with the appropriate values are sequentially applied to the diode and the resulting diode voltage differences are integrated by the integrator comprised in the ADC, the error in the temperature measurement caused by series resistance is canceled in the ADC, and an accurate temperature reading of the diode is obtained from the output of the ADC.

Abstract: Various embodiments of a method and apparatus for simulating temperature characteristics of a diode are disclosed. The output of a diode simulator may not depend upon its ambient temperature. Therefore, it may be used to calibrate a temperature measurement unit at any ambient temperature within its operational range regardless of the temperature to which the temperature measurement unit is to be calibrated. Even if the ambient temperature of the facility in which the calibration is performed varies during the calibration procedure, the output of the diode simulator may remain constant. These characteristics of the diode simulator may allow for calibration of a temperature measurement unit in significantly less time than by using prior art methods, which include the requirement to tightly control the temperature of one or more system components.

Abstract: An oil filtration system uses a housing having an inlet port and an outlet port connected by a series of passages arranged in an S-flow pattern. Each passage is bounded on at least one side by a membrane filter which filter channels the permeate removed from the filter out of the system through permeate ports that are attached to each filter and that pass through an end cap of the housing. A turbulence creating flange is disposed within the passages for creating turbulence of the fluid flowing through the passages in order to increase fluid interaction with the filters and thus increase the filtration ability of the membrane filters.

Abstract: A data transfer network is provided comprising a TFTP server connected in a manner to allow the transfer of data to and from a number of network devices connected to the network. The network devices have a unique address including one or more digits for identifying each of the devices within the network. The data is transferred between the server and each of the devices at a pre-determined time and the method for calculating this time is calculated by inputting one or more digits from the unique address of the device into a random number generator.

Abstract: An educational card game 10 including at least one deck of cards 20 comprising a plurality of individual cards 21 having a front face 22 and a rear face 23. The rear faces 23 are provided with a generic legend 24 and selected pairs of front faces 22 are provided with a pictorial representation 25 and a descriptive legend 26, respectively, of a related species that is covered by the generic legend 24 that appears on the rear face 23 of each playing card 21.