Patents by Inventor Scott A. Tetreault
Scott A. Tetreault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10375897Abstract: The present embodiments relate to an illuminated wreath card holder comprising a wreath form, decorative material configured to create a wreath on the form, and a plurality of ornamental clamp assemblies that are attached to the wreath form and configured to releasably secure, display, and illuminate greeting cards on the wreath. Each ornamental clamp assembly comprises at least one ornamental cover, at least one clip, and at least one light that is positioned between the ornamental cover and the clip. When viewed from the front, the light is hidden behind the ornamental cover and casts a glow up onto the greeting card. The ornamental cover may be star-shaped and have a return flange at its back to which the light and clip are attached. The illuminated wreath card holder may have a power source and be packed in kit form.Type: GrantFiled: April 6, 2017Date of Patent: August 13, 2019Inventor: Scott A Tetreault
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Publication number: 20180293916Abstract: The present embodiments relate to an illuminated wreath card holder comprising a wreath form, decorative material configured to create a wreath on the form, and a plurality of ornamental clamp assemblies that are attached to the wreath form and configured to releasably secure, display, and illuminate greeting cards on the wreath. Each ornamental clamp assembly comprises at least one ornamental cover, at least one clip, and at least one light that is positioned between the ornamental cover and the clip. When viewed from the front, the light is hidden behind the ornamental cover and casts a glow up onto the greeting card. The ornamental cover may be star-shaped and have a return flange at its back to which the light and clip are attached. The illuminated wreath card holder may have a power source and be packed in kit form.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventor: Scott A. Tetreault
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Patent number: 7469395Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.Type: GrantFiled: December 7, 2007Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20080074147Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.Type: ApplicationFiled: December 7, 2007Publication date: March 27, 2008Inventors: John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Thomas Lepsic, Jagannathan Narasimhan, Scott Tetreault, Sebastian Ventrone
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Patent number: 7346875Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: GrantFiled: July 7, 2005Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6985004Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: GrantFiled: February 12, 2001Date of Patent: January 10, 2006Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6970814Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.Type: GrantFiled: March 30, 2000Date of Patent: November 29, 2005Assignee: International Business Machines CorporationInventors: Carl L. Ashley, Charles N. Choukalos, Scott A. Tetreault
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Publication number: 20050262463Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: ApplicationFiled: July 7, 2005Publication date: November 24, 2005Inventors: John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Thomas Lepsic, Jagannathan Narasimhan, Scott Tetreault, Sebastian Ventrone
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Patent number: 6792582Abstract: Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria.Type: GrantFiled: November 15, 2000Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: John M Cohn, Alvar A. Dean, David J. Hathaway, David E. Lackey, Thomas M. Lepsic, Susan K. Lichtensteiger, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6711719Abstract: In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.Type: GrantFiled: August 13, 2001Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: John Maxwell Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas Michael Lepsic, Patrick Edward Perry, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20030158714Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: ApplicationFiled: February 12, 2001Publication date: August 21, 2003Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6535016Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.Type: GrantFiled: May 11, 2001Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Charles N. Choukalos, Alvar A. Dean, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20030033580Abstract: In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.Type: ApplicationFiled: August 13, 2001Publication date: February 13, 2003Applicant: International Business Machines CorporationInventors: John Maxwell Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas Michael Lepsic, Patrick Edward Perry, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20010045842Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.Type: ApplicationFiled: May 11, 2001Publication date: November 29, 2001Applicant: IBM CorporationInventors: Charles N. Choukalos, Alvar A. Dean, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6246254Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.Type: GrantFiled: December 6, 1999Date of Patent: June 12, 2001Assignee: International Business Machines CorporationInventors: Charles N. Choukalos, Alvar A. Dean, Scott A. Tetreault, Sebastian T. Ventrone