Patents by Inventor Scott Bruce Frommer
Scott Bruce Frommer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8549235Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.Type: GrantFiled: November 15, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B Levenstein
-
Publication number: 20120297162Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.Type: ApplicationFiled: November 15, 2011Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Miles Robert Dooley, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein
-
Patent number: 7809924Abstract: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.Type: GrantFiled: March 14, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Rachel Marie Flood, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein, Michael Thomas Vaden
-
Patent number: 7603543Abstract: A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.Type: GrantFiled: February 11, 2005Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Scott Bruce Frommer, Hung Qui Le, Sheldon B. Levenstein, Anthony Saporito
-
Publication number: 20080209177Abstract: A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.Type: ApplicationFiled: May 1, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Bruce Frommer, Sheldon B. Levenstein, Bruce Joseph Ronchetti, Anthony Saporito
-
Publication number: 20080162887Abstract: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.Type: ApplicationFiled: March 14, 2008Publication date: July 3, 2008Inventors: RACHEL MARIE FLOOD, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein, Michael Thomas Vaden
-
Patent number: 7380062Abstract: A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.Type: GrantFiled: February 11, 2005Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Scott Bruce Frommer, Sheldon B. Levenstein, Bruce Joseph Ronchetti, Anthony Saporito
-
Patent number: 7360058Abstract: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.Type: GrantFiled: February 9, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Rachel Marie Flood, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein, Michael Thomas Vaden
-
Patent number: 7120784Abstract: Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.Type: GrantFiled: April 28, 2003Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Gregory William Alexander, Scott Bruce Frommer, David Stephen Levitan, Balaram Sinharoy
-
Publication number: 20040215720Abstract: Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and count cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.Type: ApplicationFiled: April 28, 2003Publication date: October 28, 2004Applicant: International Business Machines CorporationInventors: Gregory William Alexander, Scott Bruce Frommer, David Stephen Levitan, Balaram Sinharoy