Abstract: A television system 106 and display method for receiving and displaying television broadcasts having various formats. The television system resizes (106) the various received image formats for display on a common display device. Images are resized horizontally by altering the rate at which data is sampled by the television (106). Images are resized vertically by using vertical scaling algorithms which alter the number of lines in an image. Format detection may be done automatically by decoding information contained in the vertical interval of the television broadcast signal, or by counting the number of lines in each frame. The input format may be indicated by a viewer.

Abstract: A high contrast spatial light modulator (40) formed of micro-mechanical pixels (10). The supporting superstructure comprising the posts (12) and hinges (16) of the pixels (10) are shielded by an umbrella-like elevated light shield (42) extending over the hinge and posts. These light shields (42) are generally square in shape, and have edges arranged at approximately 45.degree. with respect to the incident light to minimize diffraction of light therefrom into projection optics. The upper surfaces of the shields may be anodized to achieve a non-reflective, black surface when viewed through darkfield optics. The shields (42) are fabricated using conventional semiconductor processes, which are a natural extension of the baseline process.

Abstract: A graphics data unit (17) for a digital television receiver (10) that uses a spatial light modulator (16). The graphics data unit (17) has a graphics processor (22), which offloads graphics processing tasks, such as for closed captioning and on-screen display, from a main processor (14). The graphics data unit (17) also has a character memory (24), which stores fonts for closed caption and on-screen display characters. A read-only memory (22a) stores graphics primitives. The character fonts and the graphics primitives may be adapted to compensate for staggered pixel layouts of the spatial light modulator (16).

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract: A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j).

Abstract: A sequential color system is provided in which a processor (22) is coupled to a memory (24) and a receiver (27). Images are generated by shining light from a light source (28) through a color wheel (30) and onto DMD array (26). Light from the DMD array (26) is shone on screen (32). By adjusting the speed and make-up of color wheel (30) color separation is greatly reduced or eliminated. Also there are techniques for sequential imaging which may be applied to other technologies, such as CRT technologies.

Abstract: A method for controlling a digital micromirror device 40 resulting in decreased mechanical stress, longer device lifetimes, decreased incidence of spontaneous bit reset, and increased pulse-width modulation accuracy. To reduce the device stress, the bias voltage 142 applied to the mirror 50 may be reduced after the mirror 50 has been latched. To prevent premature mirror changes, the address electrode bias voltage 140 may be reduced after the mirror is driven to the desired position. To ensure that the mirror 50 returns to the neutral position during reset, the mirror bias voltage 142 may be raised from ground potential to approximately halfway between the two addressing voltages during the reset period 152. To reduce the effects of hinge memory and to ensure that the mirror 50 rotates toward the proper address electrode, the mirror bias voltage 142 may be gradually increased to allow the mirror 50 time to rotate towards the proper address electrode.