Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: Data transfers from the peripheral interface of a disk array to a data buffer are snooped to determine if the starting address of a data transfer matches an entry in a list of starting addresses for requested data. If a match is identified, third party transfer is initiated and the data is simultaneously transferred to the host interface of the host system. The resulting data bandwidth is increased. A throttling/suspension mechanism can temporarily or indefinitely hold up actual data movement into the data buffer to allow for temporary buffering and interface speed matching as data is transferred to the host interface.

Abstract: A data structure contains sequence number metadata which identifies an input/output (I/O) operation such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and also contains revision number metadata which identifies a subsequent I/O operation such as a read modify write on only a fractional component of the entire user data. The sequence number and revision number metadata are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error to a portion of the stripe is detected by a difference in sequence numbers for all of the components of data. An error arising after an I/O operation is detected by a revision number which is different from the correct revision number.

Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number.

Abstract: Apparatus and method for testing of memory locations containing both test data and test check bits are provided. The apparatus includes a memory controller that communicates with memory devices. In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data. The test data and test check bits are written to desired memory locations of the memory devices. The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations. The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read. Any lack of correspondence is indicative of one or more memory location faults.