Patents by Inventor Scott E. Thompson
Scott E. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8541824Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: GrantFiled: July 19, 2012Date of Patent: September 24, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8530286Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.Type: GrantFiled: December 17, 2010Date of Patent: September 10, 2013Assignee: SuVolta, Inc.Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
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Publication number: 20130181298Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: ApplicationFiled: March 6, 2013Publication date: July 18, 2013Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Publication number: 20130154739Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.Type: ApplicationFiled: February 19, 2013Publication date: June 20, 2013Inventors: Lawrence T. Clark, Scott E. Thompson
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Patent number: 8461875Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.Type: GrantFiled: February 18, 2011Date of Patent: June 11, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Lawrence T. Clark
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Patent number: 8421162Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: GrantFiled: September 30, 2010Date of Patent: April 16, 2013Assignee: Suvolta, Inc.Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Patent number: 8400219Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.Type: GrantFiled: March 24, 2011Date of Patent: March 19, 2013Assignee: Suvolta, Inc.Inventors: Lawrence T. Clark, Scott E. Thompson
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Publication number: 20130020638Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: SUVOLTA, INC.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20130020639Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: Suvolta, IncInventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20120299111Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: July 19, 2012Publication date: November 29, 2012Applicant: SUVOLTA, INC.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20120242409Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.Type: ApplicationFiled: March 24, 2011Publication date: September 27, 2012Inventors: Lawrence T. Clark, Scott E. Thompson
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Patent number: 8273617Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.Type: GrantFiled: February 18, 2010Date of Patent: September 25, 2012Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20110309447Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.Type: ApplicationFiled: December 17, 2010Publication date: December 22, 2011Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
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Publication number: 20110248352Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.Type: ApplicationFiled: December 17, 2010Publication date: October 13, 2011Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
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Publication number: 20110074498Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.Type: ApplicationFiled: February 18, 2010Publication date: March 31, 2011Applicant: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 7723720Abstract: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.Type: GrantFiled: November 9, 2005Date of Patent: May 25, 2010Assignee: University of Florida Research Foundation, Inc.Inventors: Toshikazu Nishida, Scott E. Thompson, Al Ogden, Kehuey Wu
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Publication number: 20090072371Abstract: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.Type: ApplicationFiled: November 9, 2005Publication date: March 19, 2009Applicant: University of Florida Research Foundation, Inc.Inventors: Toshikazu Nishida, Scott E. Thompson, Al Ogden, Wu Kehuey
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Patent number: 6020244Abstract: An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.Type: GrantFiled: December 30, 1996Date of Patent: February 1, 2000Assignee: Intel CorporationInventors: Scott E. Thompson, Paul A. Packan, Tahir Ghani, Mark Stettler, Shahriar S. Ahmed, Mark T. Bohr
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Patent number: 5877072Abstract: A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.Type: GrantFiled: March 31, 1997Date of Patent: March 2, 1999Assignee: Intel CorporationInventors: Ebrahim Andideh, Scott E. Thompson
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Patent number: 5874344Abstract: A two step source/drain annealing process which permits a dopant to be ion implanted directly into the silicon without a protective oxide. The gate oxide is removed before the ion implantation of the dopant occurs, thus the dopant is implanted directly into bare silicon. In a first step of the annealing process, a thin oxide is grown over the source and drain regions at a relatively low temperature (e.g., 600.degree. C.) this temperature to prevent the evaporation of the dopant from the silicon substrate and polysilicon gate. The second step of the annealing process occurs at a higher temperature allowing the dopant to be driven into the substrate forming the source and drain regions.Type: GrantFiled: December 30, 1996Date of Patent: February 23, 1999Assignee: Intel CorporationInventors: Scott E. Thompson, Chai-Hong Jan