Patents by Inventor Scott H. Beasor

Scott H. Beasor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833067
    Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Scott H. Beasor, Zhenyu Hu
  • Patent number: 10818557
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Patent number: 10797049
    Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
  • Publication number: 20200135723
    Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
  • Patent number: 10600914
    Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren, Hui Zang, Scott H. Beasor, Ruilong Xie
  • Publication number: 20200013678
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Publication number: 20190221661
    Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren, Hui Zang, Scott H. Beasor, Ruilong Xie