Patents by Inventor Scott Haban
Scott Haban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8966233Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.Type: GrantFiled: September 18, 2009Date of Patent: February 24, 2015Assignee: Silicon Laboratories Inc.Inventors: Scott Haban, G. Tyson Tuttle, Gregory A. Hodgson
-
Patent number: 8521099Abstract: A transceiver includes a processor, which is adapted to in a transmit mode of the transceiver, form at least part of a transmitter and in a receive mode of the transceiver, form at least part of a receiver. The transceiver may include at least one analog-to-digital converter to provide digital signals to the processor in both the transmit and receive modes of operation; and the transceiver may include at least one digital-to-analog converter to receive digital signals from the processor in the transmit and receive modes of operation. The processor may be fabricated on an integrated circuit with at least one of the analog-to-digital converters and/or with at least one of the digital-to-analog converters.Type: GrantFiled: June 29, 2007Date of Patent: August 27, 2013Assignee: Silicon Laboratories Inc.Inventors: Lawrence Der, George Tyson Tuttle, Alessandro Piovaccari, Chunyu Xin, Scott Haban, Javier Elenes, Dan Kasha, Peter Vancorenland
-
Patent number: 8264387Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.Type: GrantFiled: March 31, 2006Date of Patent: September 11, 2012Assignee: Silicon Laboratories Inc.Inventors: Lawrence Der, George Tyson Tuttle, Alessandro Piovaccari, Chunyu Xin, Scott Haban, Javier Elenes, Dan Kasha, Peter Vancorenland
-
Patent number: 8151029Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.Type: GrantFiled: December 30, 2010Date of Patent: April 3, 2012Assignee: Silicon Laboratories Inc.Inventors: Scott Haban, Dylan Hester, Ruifeng Sun
-
Patent number: 8024392Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.Type: GrantFiled: May 9, 2007Date of Patent: September 20, 2011Assignee: nCipher Corporation LimitedInventors: Greg North, Scott Haban, Kyle Stein
-
Publication number: 20110099310Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.Type: ApplicationFiled: December 30, 2010Publication date: April 28, 2011Inventors: Scott Haban, Dylan Hester, Ruifeng Sun
-
Patent number: 7882282Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.Type: GrantFiled: May 21, 2008Date of Patent: February 1, 2011Assignee: Silicon Laboratories Inc.Inventors: Scott Haban, Dylan Hester, Ruifeng Sun
-
Publication number: 20100009640Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Inventors: Scott Haban, G. Tyson Tuttle, Gregory A. Hodgson
-
Publication number: 20090292843Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Inventors: Scott Haban, Dylan Hester, Ruifeng Sun
-
Patent number: 7613913Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.Type: GrantFiled: March 21, 2006Date of Patent: November 3, 2009Assignee: Silicon Laboratories Inc.Inventors: Scott Haban, G. Tyson Tuttle, Gregory A. Hodgson
-
Publication number: 20090119358Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.Type: ApplicationFiled: May 9, 2007Publication date: May 7, 2009Inventors: Greg North, Scott Haban, Kyle Stein
-
Publication number: 20080049817Abstract: A transceiver includes a processor, which is adapted to in a transmit mode of the transceiver, form at least part of a transmitter and in a receive mode of the transceiver, form at least part of a receiver. The transceiver may include at least one analog-to-digital converter to provide digital signals to the processor in both the transmit and receive modes of operation; and the transceiver may include at least one digital-to-analog converter to receive digital signals from the processor in the transmit and receive modes of operation. The processor may be fabricated on an integrated circuit with at least one of the analog-to-digital converters and/or with at least one of the digital-to-analog converters.Type: ApplicationFiled: June 29, 2007Publication date: February 28, 2008Applicant: Silicon Laboratories, Inc.Inventors: Lawrence Der, George Tuttle, Alessandro Piovaccari, Chunyu Xin, Scott Haban, Javier Elenes, Dan Kasha, Peter Vancorenland
-
Publication number: 20070232239Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Lawrence Der, George Tuttle, Alessandro Piovaccari, Chunyu Xin, Scott Haban, Javier Elenes, Dan Kasha, Peter Vancorenland
-
Publication number: 20070226477Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Inventors: Scott Haban, G. Tuttle, Gregory Hodgson
-
Patent number: 7233970Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.Type: GrantFiled: February 16, 2002Date of Patent: June 19, 2007Assignee: Cipher Corporation LimitedInventors: Greg North, Scott Haban, Kyle Stein
-
Patent number: 6779125Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency.Type: GrantFiled: June 9, 2000Date of Patent: August 17, 2004Assignee: Cirrus Logic, Inc.Inventor: Scott Haban
-
Publication number: 20020191450Abstract: A method, system, and apparatus for performing computations.Type: ApplicationFiled: February 16, 2002Publication date: December 19, 2002Inventors: Greg North, Scott Haban, Kyle Stein