Patents by Inventor Scott Hilker
Scott Hilker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170147288Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.Type: ApplicationFiled: December 27, 2016Publication date: May 25, 2017Inventor: Scott Hilker
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Patent number: 9557963Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.Type: GrantFiled: August 12, 2015Date of Patent: January 31, 2017Assignee: Advanced Micro Devices, Inc.Inventor: Scott Hilker
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Patent number: 9317250Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.Type: GrantFiled: November 12, 2012Date of Patent: April 19, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Kelvin D. Goveas, Debjit Das Sarma, Scott A. Hilker, Hanbing Liu
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Publication number: 20150347090Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventor: Scott Hilker
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Patent number: 9141337Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.Type: GrantFiled: September 6, 2011Date of Patent: September 22, 2015Assignee: Advanced Micro Devices, Inc.Inventor: Scott Hilker
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Patent number: 8996601Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.Type: GrantFiled: June 21, 2012Date of Patent: March 31, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Scott A. Hilker, George Q. Phan
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Patent number: 8838664Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.Type: GrantFiled: June 29, 2011Date of Patent: September 16, 2014Assignee: Advanced Micro Devices, Inc.Inventors: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
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Publication number: 20140136587Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.Type: ApplicationFiled: November 12, 2012Publication date: May 15, 2014Inventors: Kelvin D. Goveas, Debjit Das Sarma, Scott A. Hilker, Hanbing Liu
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Publication number: 20130346463Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Scott A. Hilker, George Q. Phan
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Publication number: 20130282784Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.Type: ApplicationFiled: June 19, 2013Publication date: October 24, 2013Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker
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Patent number: 8495121Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.Type: GrantFiled: November 20, 2008Date of Patent: July 23, 2013Assignee: Advanced Micro Devices, Inc.Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker
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Patent number: 8407271Abstract: An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.Type: GrantFiled: August 28, 2009Date of Patent: March 26, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Kevin Hurd, Daryl Lieu, Kelvin Goveas, Scott Hilker
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Publication number: 20130060828Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.Type: ApplicationFiled: September 6, 2011Publication date: March 7, 2013Inventor: Scott Hilker
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Publication number: 20130007075Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
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Patent number: 8316071Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.Type: GrantFiled: May 27, 2009Date of Patent: November 20, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Kevin A. Hurd, Scott A. Hilker
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Publication number: 20120278591Abstract: A microprocessor is provided that has a datapath that is split into upper and lower portions. The microprocessor includes a centralized crossbar switch module having a single data movement module. The data movement module is capable of processing instructions that require operands to be exchanged between upper and lower 64-bit halves of the split architecture. The data movement module can access and process all instructions that require simultaneous access to the entire register contents of the upper and lower portions. The data movement module is configured to execute any one of a number of different instructions to perform data manipulation with respect to one or more “split-operands” (also referred to simply as “operands” herein). The data movement module can exchange data (bytes and/or bits) of operands for the upper and lower 64-bit halves so that bytes and/or bits of operands can be moved or rearranged to other positions during execution of a particular instruction.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Scott HILKER, Kevin HURD, Mark GIBSON, Jonathan CHOY
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Publication number: 20120265793Abstract: A merged compressor flip-flop circuit is provided.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: George Q. PHAN, Scott A. HILKER
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Publication number: 20110208951Abstract: A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register file to access a first portion of the instruction operand. A second portion of the execution unit provides a second access request to a second access port of the register file to access a second portion of the instruction operand. The register file can be configured into physically separate portions.Type: ApplicationFiled: February 22, 2010Publication date: August 25, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventor: Scott A. Hilker
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Publication number: 20110055307Abstract: An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Inventors: Kevin Hurd, Daryl Lieu, Kelvin Goveas, Scott Hilker
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Publication number: 20100306301Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.Type: ApplicationFiled: May 27, 2009Publication date: December 2, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Kevin A. Hurd, Scott A. Hilker