Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: In accordance with an embodiment the invention, there is a device manufacturing method. The method can comprise providing a substrate comprising a radiation-sensitive material disposed thereon and directing a beam of radiation through an aperture such that the radiation produces at least two illumination poles. The method can also comprise exposing the substrate to the at least two illumination poles using off-axis illumination and varying a size of a first illumination pole of the at least two illumination poles with respect to a second illumination pole of the at least two illumination poles.

Abstract: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.

Abstract: Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.

Abstract: Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting sub-resolution assist feature intersects a segmented sub-resolution assist feature at an intersection. Each sub-resolution assist feature is represented by an axis of the sub-resolution assist feature. The length of at least one axis is established, and an axis is modified in accordance with the length. Each axis is converted to a sub-resolution assist feature to yield the modified merged sub-resolution assist features.

Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.

Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.

Abstract: A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Abstract: A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.

Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Abstract: A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.

Abstract: A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.

Abstract: A bond pad support structure for a semiconductor device comprises at least two metal layers subjacent an uppermost passivation layer on the device. An opening through the passivation layer exposes a top surface of a top metal layer. A metal feature is formed in an insulating layer, disposed between the two metal layers, and divides the insulating layer into a plurality of discrete sections. The metal feature includes a plurality of intersecting metal-filled recesses that interconnect the two metal layers. At least a portion of the metal feature is disposed within a cross-sectional area defined as a perimeter of a periphery of the opening.

Abstract: A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.

Abstract: The present invention provides a method of forming a dynamic template with a focused beam. The method includes forming a desired template that represents a desired image, forming an actual template that represents an actual image, such as a photolithographic mask or a semiconductor device feature, and comparing the desired template to the actual template to yield a deviation template. In one embodiment the deviation template is formed by subtracting the actual template from the desired template.

Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Abstract: A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.

Abstract: A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.