Patents by Inventor Scott Jewler

Scott Jewler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10192802
    Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Scott Jewler
  • Publication number: 20170365537
    Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 21, 2017
    Inventor: Scott JEWLER
  • Patent number: 9786574
    Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Scott Jewler
  • Publication number: 20160343633
    Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 24, 2016
    Inventor: Scott JEWLER
  • Patent number: 5790381
    Abstract: SIP or ZIP packages are provided with locking elements of snap fasteners, or have package alignment tabs to combine several IC packages into an IC package assembly. Using a DIP printed circuit board socket, a high density DIP module, for example, a high capacity memory chip, is assembled. The leads of the module are inserted into a motherboard that carries the external conductors to be connected with the inner circuits of the package assembly, and soldered to the motherboard. To make the IC package assembly compatible with a conventional DIP socket, a plastic spacer can be provided between the IC packages. A retaining clip may be used to allow the IC package assembly to be repeatedly inserted and removed to and from the socket without the risk of falling apart.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 4, 1998
    Assignee: Mitsubishi Semiconductor America, Inc.
    Inventors: Nour Eddine Derouiche, Scott Jewler
  • Patent number: 5623395
    Abstract: SIP or ZIP packages are provided with locking elements of snap fasteners that allow several packages to be attached to each other to produce an IC package assembly. Using a DIP printed circuit board socket, a high density DIP module, for example, a high capacity memory chip, is assembled. The leads of the module are inserted into a motherboard that carries the external conductors to be connected with the inner circuits of the package assembly, and soldered to the motherboard. To make the IC package assembly compatible with a conventional DIP socket, a plastic spacer can be provided between the IC packages. A retaining clip may be used to allow the IC package assembly to be repeatedly inserted and removed to and from the socket without the risk of falling apart.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: April 22, 1997
    Assignee: Mitsubishi Semiconductor America, Inc.
    Inventors: Nour E. Derouiche, Scott Jewler