Abstract: A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.

Abstract: The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ.

Abstract: An improved pin clamp is described. According to one embodiment of the invention, a pin clamp circuit with improved undershoot clamping characteristics is provided. The clamp circuit actively senses the pin voltage and enhances this voltage so as to cause a voltage-to-current converter to transmit an increased amount of clamp current, relative to prior art passive clamps, to the device pin for a given amount of pin undershoot. As a result, the pin undershoot is clamped more effectively than has been the case with passive clamps. Further, since more clamp current may pass for a given voltage-to-current converter size, smaller clamp circuit components may be used. The clamp circuit according to the invention may be used generally with integrated circuit devices, but it is particularly useful in applications where bipolar devices are not available or might create adverse effects.