Abstract: A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0?i?(n?1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.

Abstract: A variable-gain amplifier includes an intermediate node operative to receive an electric current from a current source. A common-emitter amplifier has a collector electrically connected to the intermediate node. A first common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to an output node. A base-degenerated amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to the output node. A second common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to small-signal ground.

Abstract: Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which includes a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Abstract: An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.

Abstract: A sub-harmonic mixer includes a first transistor having a source and a drain and a second transistor having a source connected to the source of the first transistor and a drain connected to the drain of the first transistor. A mixing transistor is configured to be biased in a linear operating region. The mixing transistor includes a drain coupled to the sources of the first transistor and the second transistor. The mixing transistor has its drain driven by a signal at twice a local oscillator (LO) frequency and its gate driven by a radio frequency (RF) signal while the mixing transistor is biased in the linear region such that a process of frequency doubling and mixing are performed simultaneously.

Abstract: An off-chip signal is provided to a differential branch-line directional coupler implemented entirely on-chip. The coupler produces differential quadrature signals, which are then buffered and applied to a quadrature mixer. The coupler is implemented entirely on-chip using microstrip transmission lines. The coupler is made up of a plurality of rings and a plurality of underpasses connecting ports of the rings, wherein each of the plurality of rings is made up of four branch lines, and each branch line having an electrical length of one-quarter wavelength at the center design frequency. Coupling between the plurality of branch lines of the rings may be varied.

Abstract: A transverse form analog finite impulse response filter. The filter has an input and an output. A first set of passive delay elements connected in serial to the input, and a second set of passive delay elements are connected in serial to the output. Transconductors are connected in parallel with the first plurality of passive delay elements and the second plurality of passive delay elements. A set of buffer amplifiers is connected to the passive delay elements in the first set of passive delay elements and in the set of passive delay elements. The buffer amplifiers cause a reduction in loss in the passive delay elements.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: Circuits and methods are provided for implementing highly efficient switch-mode power amplifiers using BJTs (bipolar junction transistors) as active switching devices at millimeter-wave frequencies. More specifically, circuits and methods are provided for driving power amplifiers with BJT switching devices to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz).

Abstract: Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which includes a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

Abstract: A method for detecting and compensating for thermal asperity in data signals, including the steps of detecting thermal asperity in the data signals and adjusting a parameter prior to amplification of the data signals.

Abstract: A circuit of a dual control voltage-controlled ring oscillator is disclosed having significantly less power and area while still maintaining a large frequency range and tune accuracy. The dual control ring oscillator has at least two delay paths which can be added or interpolated according to an interpolation variable set by a coarse tune and a fine tune code. In addition, moreover, each of the delay paths have a number of variable delay elements which are varied in response to another input code. When the variable delay elements are capacitors, the capacitance will be varied in accordance with another coarse tune code. In the preferred embodiment, the input codes are digital and the frequency range obtained can be greater than two to one. First, the variable delay elements are adjusted to obtain coarse tuning of the dual control ring oscillator then the interpolation variable is more finely adjusted to obtain fine tuning of the ring oscillator.

Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.